A semiconductor memory device is provided. The semiconductor memory device includes a memory core including a plurality of memory cells configured to store a plurality of data received from an external processor; and a statistical feature extractor disposed on a data path between the external processor and the memory core, the statistical feature extractor being configured to analyze statistical characteristics of the plurality of data, identify at least one statistical feature value associated with the statistical characteristics, store the at least one statistical feature value and transmit the at least one statistical feature value to the external processor.

Method for active data storage management to optimize use of an electronic memory. The method includes providing signal injections for data storage. The signal injections can include various types of data and sizes of data files. Response signals corresponding with the signal injections are received, and a utility of those signals is measured. Based upon the utility of the response signals, parameters relating to storage of the data is modified to optimize use of long-term high latency passive data storage and short-term low latency active data storage.

In one embodiment, an apparatus is provided. The apparatus includes a printed circuit board. The apparatus also includes a first connector coupled to the printed circuit board. The first connector is configured to couple the apparatus to a computing device. The apparatus further includes a second connector coupled to the printed circuit board. The second connector is configured to couple the apparatus to a data storage device. The apparatus further includes a securement mechanism comprising a first portion and a second portion. The securement mechanism is movable about the apparatus between a first position and a second position. The first portion is configured to maintain the securement mechanism at the first position. The second portion is configured to secure the data storage device to the apparatus when the securement mechanism is in the first position.

A data management apparatus, a data management method, and a data storage device are provided. The data management apparatus includes a management unit and a data migration unit. The management unit manages data transmission channels between two types of storage media with different transmission performance. Then, the data migration unit migrates data between the two types of storage media through the managed data transmission channels. In this way, the data management apparatus can directly migrate data between storage media with different transmission performance, and a CPU in a system does not need to perform processing such as instruction conversion and protocol conversion, so that a delay of performing the foregoing processing by the CPU can be shortened. In addition, because the CPU does not need to perform data migration, resource overheads of the CPU can be reduced.

Embodiments of the present disclosure provide a system for accelerated data search of a database storage system. The system includes a host device including a database storage engine; and a memory system including a controller and a memory device, which includes a plurality of pages storing multiple records. The controller includes a page processing accelerator configured to: read, from the plurality of pages, multiple pages in response to a filtered read command; filter particular pages among the multiple pages based on a column full search condition, the filtered pages including entries satisfying the column full search condition; and transfer, to the host device, information regarding the filtered pages.

Aspects include obtaining data to be transformed. A selected transformation to be applied to the data is determined based on a storage block address list entry (SBALE) in a storage block address list (SBAL). The SBALE includes at least one field that is used in determining the selected transformation to be applied. The selected transformation is applied on the data to generate transformed data and the transformed data is placed in a location specified by the SBAL.

A computational storage device includes a non-volatile memory (NVM) device; and a storage controller configured to control the NVM device. The storage controller includes: a computation processor configured to execute an internal application to generate an internal command; a host interface circuit configured to receive a host command from an external host device, to receive the internal command from the computation processor, and to individually process the received host command and the received internal command; a flash translation layer (FTL) configured to perform an address mapping operation based on a result of the processing of the host interface circuit; and a memory interface circuit configured to control the NVM device based on the address mapping operation of the FTL.

A storage device comprises first and second storage devices mounted on respective first and second PCBs (Printed Circuit Boards) that are separated from each other, the first and second PCBs configured to store different data. The first storage device includes a first storage controller, and a first shock sensor that senses an impact of the first storage device to output a first sensor signal. The second storage device includes a second shock sensor different from the first shock sensor, and senses an impact of the second storage device to output a second sensor signal. The first storage controller outputs a first internal control signal that controls an internal operation of the first storage device based on the first sensor signal. The first storage device and the second storage device transmit data to each other based on the first sensor signal and the second sensor signal.

According to one embodiment, a memory system includes a nonvolatile memory and a controller. In response to receiving from a host a write request designating a first address for identifying data to be written, the controller encrypts the data with the first address and a first encryption key, and writes the encrypted data to the nonvolatile memory together with the first address. In response to receiving from the host a read request designating a physical address indicative of a physical storage location of the nonvolatile memory, the controller reads both the encrypted data and the first address from the nonvolatile memory on the basis of the physical address, and decrypts the read encrypted data with the first encryption key and the read first address.

A storage device and a storage system including the same are provided. The storage device includes a reference clock pin configured to receive a reference clock signal from a host, a reference clock frequency determination circuitry configured to determine a reference clock frequency from the reference clock signal received through the reference clock pin, and a device controller circuitry configured to perform a high speed mode link startup between the host and the storage device according to the reference clock frequency.