A memory controller controlling an operation of a memory device including a plurality of memory cells may provide a first suspend command instructing the memory device to suspend performance of the first operation, provide a command requesting information on a target period in which the first operation is suspended among the plurality of periods, provide a command instructing a second operation to the memory device, provide a resume command instructing the memory device to resume the performance of the first operation after the second operation is ended and provide a second suspend command instructing the memory device to re-suspend the performance of the first operation after a delay elapses from a time at which the resume command is provided, the delay being based on the delay information corresponding to the target period.

A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.

In-vehicle detection system includes nonvolatile memory, a controller (SoC) that reads and writes data from and in nonvolatile memory, and detector that outputs detection information to SoC. SoC changes a control signal of nonvolatile memory in accordance with the output of detector.

A memory system includes a non-volatile memory device and a controller. The non-volatile memory device performs operations in parallel on a plurality of memory blocks. The controller determines, in response to a read request on a plane including a target memory block among the plurality of memory blocks, whether to perform a process for a partial suspension on the operations based on suspension counts of the plurality of memory blocks. The controller controls, when performing a process for the partial suspension, the non-volatile memory device to suspend the operation being performed on the target memory block and to keep performing the operations being performed on other memory blocks among the plurality of memory blocks.

A method and apparatus for sustaining performance of a data storage device by predictively determining resource needs and executing processes to meet those needs before the resources are actually needed. According to certain embodiments, a controller collects commands coming from a host and provides these to a machine learning model such as a recurrent neural network (RNN). The RNN is trained using this data, and output of the trained model is used to predict future commands. As future commands are developed by the RNN, resource allocation processes such as garbage collection may be initiated prior to the actual need, during times when processing cycles in the data storage device are available. By operating the garbage collection when the device has available processing may mitigate transition to an urgent mode.

Technologies for switching network traffic include a network switch. The network switch includes one or more processors and communication circuitry coupled to the one or more processors. The communication circuitry is capable of switching network traffic of multiple link layer protocols. Additionally, the network switch includes one or more memory devices storing instructions that, when executed, cause the network switch to receive, with the communication circuitry through an optical connection, network traffic to be forwarded, and determine a link layer protocol of the received network traffic. The instructions additionally cause the network switch to forward the network traffic as a function of the determined link layer protocol. Other embodiments are also described and claimed.

A processing device, operatively coupled with a memory component, is configured to provide a plurality of virtual memory controllers and to provide a plurality of physical functions, wherein each of the plurality of physical functions corresponds to a different one of the plurality of virtual memory controllers. The processing device further presents the plurality of physical functions to a host computing system over a peripheral component interconnect express (PCIe) interface, wherein each of the plurality of physical functions corresponds to a different virtual machine running on the host computing system, and manages input/output (IO) operations received from the host computing systems and directed to the plurality of physical functions, as well as background operations performed on the memory component, in view of class of service parameters associated with the plurality of physical functions.

A storage device includes a semiconductor memory device including memory blocks, planes which include the memory blocks and memory dies in which the planes are included; and a controller configured to store user data and metadata determined based on a command received from a host, in super memory blocks each including some of the memory blocks. The controller includes a segment queuing circuit configured to queue segments of the user data or the metadata to N (N is a natural number) virtual die queues according to a striping scheme; and a segment storage circuit configured to store the queued segments of the user data or the metadata in a super memory block among the super memory blocks, wherein the queued segments of the user data or the metadata are stored in the memory blocks included in the super memory block, according to a striping scheme.

The invention introduces a method for verifying memory interface, performed by a processing unit, to include: driving a physical layer of a memory interface to pull-high or pull-low a signal voltage on each Input-Output (IO) pin thereof to a preset level according to a setting; obtaining a verification result corresponding to each IO pin from the memory interface; and storing each verification result in a static random access memory (SRAM), thereby enabling a testing host to obtain each verification result of the SRAM through a test interface. The testing host may examine each verification result to know whether any unexpected error has occurred in signals on the IO pins of the memory interface.

A storage system includes a plurality of storage controllers and a drive box including one or more non-volatile storage devices. The drive box includes a memory on which reading and writing are performed in a unit different from a unit for reading and writing the one or more non-volatile storage devices, and which stores control information to be used by the plurality of storage controllers, and a memory controller that enables each storage controller of the plurality of storage controllers to exclusively read and write the control information of the memory by arbitrating accesses to the memory from the plurality of storage controllers.