A method of storing data, a method of reading data, a device, and a storage medium are provided, which relate to a field of artificial intelligence, in particular to the fields of cloud computing technology and distributed storage technology. A specific implementation scheme includes: storing at least one target data into a target file in a storage class memory device; recording a storage address of the at least one target data in the storage class memory device in a dynamic random access memory as a first index data; and synchronously storing the first index data into the storage class memory device as a second index data.

A method for computational storage may include receiving, at a storage device, a modified version of a portion of data, generating, at the storage device, a restored portion of data from the modified version of the portion of data, and performing, at the storage device, an operation on the restored portion of data. The method may further include receiving, at the storage device, a request to perform the operation on the portion of data. The generating may include decompressing the modified version of the portion of data. The generating may include decrypting the modified version of the portion of data. The method may further include sending, from the storage device, a result of the operation on the restored portion of data. The operation may include a filtering operation. The operation may include a scanning operation. The method may further include dividing data to generate the portion of data.

Aspects of the disclosure are directed to hardware interconnects and corresponding devices and systems for non-coherently accessing data in shared memory devices. Data produced and consumed by devices implementing the hardware interconnect can read and write directly to a memory device shared by multiple devices, and limit coherent memory transactions to relatively smaller flags and descriptors used to facilitate data transmission as described herein. Devices can communicate less data on input/output channels, and more data on memory and cache channels that are more efficient for data transmission. Aspects of the disclosure are directed to devices configured to process data that is read from the shared memory device. Devices, such as hardware accelerators, can receive data indicating addresses for different data buffers with data for processing, and non-coherently read or write the contents of the data buffers on a memory device shared between the accelerators and a host device.

An apparatus comprising an input to couple to a negative voltage source; and circuitry to detect whether the input has crossed a negative voltage threshold, wherein the circuitry comprises a first capacitor that is selectively coupled to the first input and a second capacitor that is selectively coupled to a second input coupled to a positive voltage source.

A method for memory access may include receiving, at a device, a first memory access request for a parallel workload, receiving, at the device, a second memory access request for the parallel workload, processing, by a first logical device of the device, the first memory access request, and processing, by a second logical device of the device, the second memory access request. Processing the first memory access request and processing the second memory access request may include parallel processing the first and second memory access requests. The first logical device may include one or more first resources. The method may further include configuring the first logical device based on one or more first parameters of the parallel workload. The method may further include allocating one or more first resources to the first logical device based on at least one of the one or more first parameters of the parallel workload.

A reconfigurable compute fabric of a system can include multiple nodes, and each node can include multiple, communicatively coupled tiles with respective processing and storage elements. In an example, a tile-based processor can be configured to perform operations comprising receiving a first stencil that defines input data for a first operation. The stencil can have a height corresponding to N rows in a main memory and a stencil width corresponding to M columns in the main memory. The processor can perform operations comprising establishing N buffers in a tile memory, each buffer having M buffer elements, and populating the M buffer elements of the N buffers using respective information, defined by the first stencil, from the main memory. Tile-based stencil operations can use information from the N buffers and provide compute results in an output array.

An illustrative method includes receiving a write request to write payload data to a virtual storage volume; transmitting the write request to a plurality of storage nodes each storing a replica of the virtual storage volume; acknowledging the write request only after a quorum of the storage nodes has stored the payload in their respective kernel memory; and flushing the payloads stored in each kernel memory to persistent storage only after a threshold number of outstanding write requests that have been acknowledged, but not yet flushed, has been reached, the flushing configured to optimize performance for synchronous workloads.

Methods, systems, and devices for techniques for managing temporarily retired blocks of a memory system are described. In some examples, aspects of a memory system or memory device may be configured to determine an error for a block of memory cells. For example, a controller may determine an existence of the error and may temporarily retire the block. A media management operation may be performed on the temporarily retired block and, depending on one or more characteristics of the error, the temporarily retired block may be enabled or retired.

A vehicle memory sub-system can be switched from a normal mode to a pre-shutdown mode and initiate a media management operation before shutting down. The mode switch and/or media management operation can be performed in response to receiving a shutdown or pre-shutdown command for the vehicle. After completion of the memory management operation the vehicle and/or memory sub-system can be shutdown.

A memory controller, a memory system and a method of operating a memory controller controlling a memory device are described. The memory controller may include a workload manager in communication with the memory device in which data is written and is read, the workload manager configured to acquire an amount of write data written to the memory device during a preset reference time, calculate a workload parameter indicating a ratio of the amount of write data to a reference write amount, and store the workload parameter for the preset reference time, and a performance manager configured to control, based on the workload parameter, a certain background operation performed by the memory device during a period corresponding to the workload parameter.