A data storage device includes a non-volatile memory device including a memory block having a number of memory dies, and a controller coupled to the memory device. A memory access command is received and a memory access operation based on the received command is performed. A number of bytes transferred during the memory access operation is determined, and the determined number of bytes is analyzed to determine whether the number of transferred bytes is equal to a predetermined number. A transfer status fail bit is set if the number of transferred bytes is not equal to the predetermined number.

A processing device in a memory system identifies a first set of bits associated with a translation unit of a memory device, wherein the first set of bits correspond to a page field. The processing device identifies a second set of bits associated with the translation unit of the memory device, wherein the second set of bits corresponds to a block field. The processing device determines that a value representing a page number stored in the page field satisfies a threshold criterion. Responsive to determining that the value representing the page number satisfies the threshold criterion, the processing device determines a difference between the value representing the page number and a threshold value associated with the threshold criterion plurality of block stripes on a memory device. The processing device stores a value representing the difference as a plurality of bits of the second set of bits. The processing device stores a value representing a block number stored in the block field as a plurality of bits of the first set of bits.

Examples described herein relate to a network interface device comprising an interface to memory and circuitry. In some examples, the circuitry is to: determine a number of data units stored in a page in the memory and based on no data unit stored in a page of memory, permit storage of a data unit in the page in the memory.

A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to interact with a host device using Universal Flash Storage (UFS) interface protocols, provide a hint to the host device, switch between a first mode and a second mode, retrieve the data from the memory device, and deliver the data to the host device. The hint includes an indication of what order data will be received from the data storage device. The order of the data will be in a different order than a requested order after providing the hint.

A memory device includes a memory array of memory cells and control logic operatively coupled to the memory array. The control logic to perform memory erase operations including: performing a true erase sub-operation by causing multiple pulse steps to be applied sequentially to a group of memory cells of the memory array, wherein each sequential pulse step of the multiple pulse steps occurs during a pulse-step period and at a higher voltage compared to an immediately-preceding pulse-step; in response to detecting an erase suspend command during a pulse step, suspending the true erase sub-operation at a start of a subsequent pulse-step period after the pulse step; and resuming the true erase sub-operation at an end of the subsequent pulse-step period.

Exemplary methods, apparatuses, and systems include receiving a plurality of read operations. The read operations are divided into a current set of a sequence of read operations and one or more other sets. The size of the current set is a first number of read operations. An aggressor read operation is selected from the current set. A first data integrity scan is performed on a victim of the aggressor and a first indicator of data integrity is determined based on the first data integrity scan. A scaling factor is determined using the indicator of data integrity and a number of program erase cycles for the portion of memory. The set size of read operations is adjusted to a second number of read operations using the scaling factor for a subsequent set.

Embodiments of the present disclosure provide a system for testing multicore firmware (FW) in a memory system and a method thereof. A test system includes a test device and a storage device including a plurality of flash translation layer (FTL) cores, each FTL core associated with multiple memory blocks. The test device generates test preconditions for the plurality of FTL cores and provides the test preconditions to the plurality of FTL cores, the test preconditions being different from each other. Each of the plurality of FTL cores performs one or more test operations based on a corresponding test precondition of the test preconditions.

A memory controller circuit is disclosed which is coupleable to a first memory circuit, such as DRAM, and includes: a first memory control circuit to read from or write to the first memory circuit; a second memory circuit, such as SRAM; a second memory control circuit adapted to read from the second memory circuit in response to a read request when the requested data is stored in the second memory circuit, and otherwise to transfer the read request to the first memory control circuit; predetermined atomic operations circuitry; and programmable atomic operations circuitry adapted to perform at least one programmable atomic operation. The second memory control circuit also transfers a received programmable atomic operation request to the programmable atomic operations circuitry and sets a hazard bit for a cache line of the second memory circuit.

A memory system includes: a memory device; a first queue suitable for queuing commands received from a host; a second queue suitable for enqueuing the commands from the first queue and dequeuing the commands to the memory device according to the FIFO scheme; and a processor suitable for: delaying enqueuing a read command into the second queue until the program operation is successfully performed when a logical address of a write command, in response to which a program operation is being performed, is the same as a logical address corresponding to the read command enqueued in the first queue; and determining whether or not to enqueue a subsequent read command, which is enqueued in the first queue after the read command, into the second queue.

A degree of fragmentation is determined based on a number of holes present in a storage system layout or a portion of a layout. Edges between the holes and used portions of the storage system are tabulated by scanning a storage space. The occurrences of a pattern of used/available allocation units and/or the occurrences of another pattern available/used allocation units are recognized. A fragmentation value is calculated based on occurrences of the patterns in view of the total storage space. The present fragmentation measurement system utilizes the number of occurrences of the holes in assessing fragmentation.