Various embodiments relate to a memory controller, including: a memory interface connected to a memory; an address and command logic connected to the memory interface and a command interface, wherein the address and control logic is configured to receive a memory read request; a memory scrubber configured to cycle through memory locations and to read data from those locations; a region selector configured to determine when a memory location read by the memory scrubber is within an integrity checked memory region; a runtime integrity check (RTIC) engine connected to a read data path of the memory interface, wherein the RTIC engine is configured to calculate an integrity check value for the RTIC region using data read from the checked memory region by the memory scrubber; and a RTIC controller configured to compare the calculated integrity check value for the checked memory region to a reference integrity check value for the checked memory region.

A system includes a memory device, and a processing device, operatively coupled to the memory device, to perform operations including receiving a request to sequentially write data to a block of a memory device, in response to receiving the request, writing the data to the block to obtain sequentially written data, initiating accumulation of logical-to-physical (L2P) mapping data corresponding to the sequentially written data, determining that a criterion for terminating the accumulation of the L2P mapping data is satisfied, in response to determining that the criterion is satisfied, terminating the accumulation of the L2P mapping data to obtain accumulated L2P mapping data, and updating an L2P mapping data structure based on the accumulated L2P mapping data.

Operation of a non-volatile memory (NVM) storage module may comprise receiving a plurality of commands as associated with a plurality of priority-based queues from a host-memory. A received command is evaluated in accordance with a priority associated with the queue storing the command and a size of the command. The evaluated command is split into a plurality of sub-commands, each of the sub-commands having a size determined in accordance with the evaluation. A predetermined number of hardware resources are allocated for each of the evaluated command based on at least the size of each of the sub-commands to thereby enable a processing of the evaluated command based on the allocated resources. Quality of service (QoS) for the evaluated-command may thus be augmented.

Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. More specifically, embodiments of the present invention are directed to an instruction set of an object memory fabric. This object memory fabric instruction set can include trigger instructions defined in metadata for a particular memory object. Each trigger instruction can comprise a single instruction and action based on reference to a specific object to initiate or perform defined actions such as pre-fetching other objects or executing a trigger program.

In one embodiment, a system may include a memory unit, a first processing unit configured to write data into a memory region of the memory unit, a second processing unit configured to read data from the memory region, a first control unit configured to control the first processing unit's access to the memory unit and, and a second control unit configured to control the second processing unit's access to the memory unit. The first control unit may be configured to obtain, from the second control unit, a first memory address associated with a data reading process of the second processing unit, receive a write request from the first processing unit, the read request having an associated second memory address, and write data into the memory region based on the write request in response to a determination that the second memory address falls outside of the guarded reading region.

A composite layout to store one or more extents of a data object in a first storage system and one or more extents of the data object in a second, different storage system. The first storage system may be configured for the efficient storage of small chunks of data such as, e.g., chunks of data small than the addressable block size of the storage devices used by the storage systems.

Methods, systems, and devices for the dynamic selection of cores for processing responses are described. A memory sub-system can receive, from a host system, a read command to retrieve data. The memory sub-system can include a first core and a second core. The first core can process the read command based on receiving the read command. The first core can identify the second core for processing a read response associated with the read command. The first core can issue an internal command to retrieve the data from a memory device of the memory sub-system. The internal command can include an indication of the second core selected to process the read response.

A memory architecture and a processing unit that incorporates the memory architecture and a systolic array. The memory architecture includes: memory array(s) with multi-port (MP) memory cells; first wordlines connected to the cells in each row; and, depending upon the embodiment, second wordlines connected to diagonals of cells or diagonals of sets of cells. Data from a data input matrix is written to the memory cells during first port write operations using the first wordlines and read out from the memory cells during second port read operations using the second wordlines. Due to the diagonal orientation of the second wordlines and due to additional features (e.g., additional rows of memory cells that store static zero data values or read data mask generators that generate read data masks), data read from the memory architecture and input directly into a systolic array is in the proper order, as specified by a data setup matrix.

A security solution having a system, a method, or a computer program for protecting contents in a target storage device that is arranged to be removable from a storage system having a unique combination of a system complex key (SCK) and a system identification (SID). The solution includes receiving a request to remove the target storage device from the storage system, where the storage system may have a plurality of storage devices each containing the identical combination of system complex key (SCK) and system identification (SID), and receiving a system complex key password (SCKP). The solution includes comparing the system complex key password (SCKP) to the system complex key (SCK) in the storage system, determining whether the system complex key password (SCKP) matches the system complex key (SCK) in the storage system, and suspending all read or write operations to the target storage device when the system complex key password (SCKP) matches the system complex key (SCK) in the storage system.

Systems and processes for efficient accessing, storing and transmitting of fixed data elements and dynamic data elements, each having its own native form. The data elements are organized according to a schema, with (a) all fixed data elements stored in their native forms in a fixed memory allocation, and (b) each dynamic data element stored in memory in its own native form, in its own data allocation. With this memory structure, computational overhead of converting data elements from their native forms to JSON, XML or other markup language is avoided, making accessing data (getting), updating data (setting), converting data to a serial stream for transmission or other manipulation (serializing), deserializing, and other manipulations of the data elements much more CPU efficient and requiring less bandwidth.