A split-gate flash memory, a method of fabricating the split-gate flash memory and a method for control thereof are disclosed. The split-gate flash memory includes: a semiconductor substrate including a first memory region and a second memory region that are separate from each other; and a word-line structure between the first memory region and the second memory region. The word-line structure includes, stacked on the surface of the semiconductor substrate sequentially from bottom to top, a word-line oxide layer, a read gate, a dielectric oxide layer and an erase gate. The read and erase gates can each function as a word line of the split-gate flash memory for enabling a read or erase operation. During the erase operation, a voltage applied on the erase gate has an insignificant impact on the underlying semiconductor substrate, which is helpful in reducing channel leakage in the semiconductor substrate.

An integrated circuit device may at least one memory cell configured for dual erase modes. Each memory cell may be configured to be erased via two different nodes, which may be selectively used (e.g., in any switched or alternating manner) to reduce the erase cycling at each individual node and thereby increase (e.g., double) the lifespan of the cell. For example, the device may include flash memory cells having a pair of program/erase nodes (e.g., an erase gate and a word line) formed over each respective floating gate, wherein the program/erase nodes are selectively used (e.g., in any switched or alternating manner) for the cell erase function.

A memory device is provided. The memory device includes a memory array of a plurality of memory elements, a plurality of word lines or word line pairs, a plurality of bit line pairs, and a plurality of common source lines. Each of the memory elements includes two memory cells. The memory device is configured for calculating an energy value based on a plurality of state signals and a plurality of coefficients, and the two memory cells of each of the memory elements are configured for performing an individual selection such that one of the two memory cells of each of the memory elements receives two corresponding state signals from a corresponding word line or a corresponding word line pair and a corresponding bit line pair and generates an output current into a corresponding common source line for calculating the energy value.

Systems, apparatuses and methods may provide for identifying a target sub-block of NAND strings to be partially or wholly erased in memory and triggering a leakage current condition in one or more target select gate drain-side (SGD) devices associated with the target sub-block. Additionally, the leakage current condition may be inhibited in one or more remaining SGD devices associated with remaining sub-blocks of NAND strings in the memory. In one example, triggering the leakage current condition in the one or more target SGD devices includes setting a gate voltage of the one or more target SGD devices to a value that generates a reverse voltage that exceeds a threshold corresponding to the leakage current condition.

A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data.

An integrated circuit device may at least one memory cell configured for dual erase modes. Each memory cell may be configured to be erased via two different nodes, which may be selectively used (e.g., in any switched or alternating manner) to reduce the erase cycling at each individual node and thereby increase (e.g., double) the lifespan of the cell. For example, the device may include flash memory cells having a pair of program/erase nodes (e.g., an erase gate and a word line) formed over each respective floating gate, wherein the program/erase nodes are selectively used (e.g., in any switched or alternating manner) for the cell erase function.

Methods of operating a memory include determining a voltage level of a plurality of voltage levels at which a memory cell is deemed to first activate in response to applying the to a control gate of that memory cell for each memory cell of a plurality of memory cells, determining a plurality of voltage level distributions from numbers of memory cells of a first subset of memory cells deemed to first activate at each voltage level of the plurality of voltage levels, determining a transition between a pair of voltage level distributions for each adjacent pair of voltage level distributions, and assigning a respective data state to each memory cell of a second subset of memory cells responsive to the determined voltage level at which that memory cell is deemed to first activate and respective voltage levels of the transitions for each adjacent pair of voltage level distributions.

Methods of operating a memory include determining a voltage level of a plurality of voltage levels at which a memory cell is deemed to first activate in response to applying the to a control gate of that memory cell for each memory cell of a plurality of memory cells, determining a plurality of voltage level distributions from numbers of memory cells of a first subset of memory cells deemed to first activate at each voltage level of the plurality of voltage levels, determining a transition between a pair of voltage level distributions for each adjacent pair of voltage level distributions, and assigning a respective data state to each memory cell of a second subset of memory cells responsive to the determined voltage level at which that memory cell is deemed to first activate and respective voltage levels of the transitions for each adjacent pair of voltage level distributions.

A TCAM comprises a plurality of first search lines, a plurality of second search lines, a plurality of memory cell strings and one or more current sensing units. The memory cell strings comprise a plurality of memory cells. The current sensing units are coupled to the memory cell strings. In a search operation, a determination that whether any of the data stored in the memory cell strings matches a data string to be searched is made according to whether the one or more current sensing units detect current from the memory cell strings, or according to the magnitude of the current flowing out from the memory cell strings detected by the one or more current sensing units. Each memory cell includes a first transistor, a second transistor and an inverter. The first search line is coupled to the second search line by the inverter.

A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data.