A computing device performs initial processing of sensor data. The computing device performs obtaining sensor data, writing the sensor data to first addresses of a dynamically allocated buffer associated with the computing device, encoding the sensor data, writing the encoded sensor data to second addresses of the dynamically allocated buffer, in response to completing the writing of the encoded sensor data, indicating that the writing of the encoded sensor data has been completed, receiving, from a computing resource, a polling request to read the encoded sensor data, transmitting, to the computing resource, a status that the writing of the encoded sensor data to the second addresses has been completed, reading, to a memory of the computing resource, the encoded sensor data, receiving, from the computing resource, a second status that the encoded sensor data has been read, and removing, from the dynamically allocated buffer, the encoded sensor data.

A computing system has a first processing device (e.g., CPU, FPGA, or GPU) and memory regions (e.g., in a DRAM device) used by the processing device during normal operation. In one approach, the computing system is configured to: collect data associated with operation of an autonomous vehicle; monitor, by a first processing device, the collected data; and based on the monitoring, determine that an event on the autonomous vehicle has occurred. The computing system is further configured to, in response to determining that the event has occurred, initiate a transfer of data controlled by a second processing device, the transfer including copying data stored in volatile memory of the autonomous vehicle to non-volatile memory of the autonomous vehicle, wherein the second processing device controls copying of the data independently of the first processing device. The computing system is also further configured to, in response to determining that the event has occurred, reduce or terminate power to the first processing device.

The application discloses a verification method and system. The verification method is for verifying content of a first volatile read-write memory of a chip. A first non-volatile read-write memory of the chip stores a firmware image, including predetermined calculation value. The chip includes a second volatile read-write memory. The verification method includes: at a bootloader mode, loading a first portion and a second portion of the firmware image to the first volatile read-write memory and the second volatile read-write memory respectively; performing a first specific operation to the first portion and the second portion to obtain a first calculation value; performing a second specific operation to the first calculation value to obtain a second calculation value and storing the second calculation value in the second volatile read-write memory.

Methods, systems, and devices for hazard detection in a multi-memory device are described. A device may receive a first command that indicates a first bank address, a first row address, and a first column address. Based on the first bank address, the device may select a buffer for a hazard detection procedure that detects hazardous commands. The device may compare, as part of the hazard detection procedure, the first row address and the first column address from the first command with a second row address and a second column address from a second command in the buffer. The device may determine whether the first command and the second command are hazardous commands based on comparing the first row address and the first column address from the first command with the second row address and the second column address from the second command.

Memory access control, as described herein, can leverage persistent memory to store data that is generally stored in a non-persistent memory. An example method for memory access control can include receiving, by control circuitry resident on a memory device, a memory access request targeting an address of a volatile (e.g., non-persistent) memory component of the memory device and determining characteristics of data associated with the targeted address. The method can further include accessing data at the targeted address of the volatile memory component in response to determining that the characteristics of the data meet a first criterion and accessing data at another address of a non-volatile memory component in response to determining that the characteristics of the data meet a second criterion.

Systems, apparatuses, and methods related to object management in tiered memory systems are discussed. An example method can include writing data representative of a memory object of a first memory device. The first memory device can include a first type of memory medium includes a NAND Flash or a NOR Flash. The example method can include determining that a data size of the memory object is less than a threshold data size. The method can include writing the data representative of the memory object to a second memory device that includes a second type of memory medium. The second memory medium is a non-volatile memory that includes phase-change memory or resistive random access memory.

Storage systems are disclosed. For instance, a storage system comprises a first storage device of a first type and a second storage device of a second type, and the first storage device has a higher access velocity than the second storage device. A threshold indicating a volume limit of data stored in the first storage device can be determined. Data, which is specified by a write request for writing data to the storage system, is written to the first storage device in response to determining the data amount in the first storage device is lower than the threshold. A read request from a client device is processed based on data stored in the first storage device. Consequently, the first storage device with a higher access velocity in the storage system may be utilized as much as possible, so that storage device latency in the storage system is managed more effectively.

Systems, methods, and apparatus related to a memory system that manages an interface for a volatile memory device and a non-volatile memory device to control memory system power. In one approach, a controller evaluates a demand on memory performance. If the demand of a current computation task needed by the host is high, a DRAM device is powered-up to meet the demand. Otherwise, if the non-volatile memory device is adequate to meet the demand, the DRAM memory is partially or fully-powered down to save power. In another approach, a task performed for a host device uses one or more resources of a first memory device (e.g., DRAM). A performance capability of a second memory device (e.g., NVRAM) is determined. A controller of the memory system determines whether the performance capability of the second memory device is adequate to service the task. In response to determining that the performance capability is adequate, the controller changes a mode of operation of the memory system so that one or more resources of the second memory device are used to service the task.

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, perform a number of intermediate operation phases of the logical operation by sensing a respective number of different memory cells coupled to the sense line, and accumulate a result of the first operation phase and the number of intermediate operation phases in a secondary latch coupled to the primary latch without performing a sense line address access.

A memory sub-system periodically performs a first wear leveling operation using a direct mapping function on a data management unit of a memory component in the memory sub-system at a first frequency. The memory sub-system further periodically performs a second wear leveling operation using indirect mapping on a group of data management units of the memory component at a second frequency, wherein the second wear leveling operation is performed less frequently than the first wear leveling operation.