A controller of a memory sub-system can, responsive to providing a command completion signal to a host, mark a portion of a plurality of commands that are addressed to a same logical block of the memory devices, reorder the marked portion of the plurality of commands, wherein write commands from the marked portion of the plurality of commands are given priority over read commands from the marked portion of the plurality of commands, execute a newest write command from the marked portion of the plurality of commands prior to executing read commands, addressed to the same logical block, from the marked portion of the plurality of commands, and execute read commands from the marked portion of the plurality of commands in on an order in which the read commands were received and after the execution of the newest write command, wherein the read commands are executed responsive to an execution of the newest write command.

A memory system includes a memory device and a controller. The memory device includes plural storage regions including plural non-volatile memory cells. The plural storage regions have a different data input/output speed. The controller is coupled to the memory device via at least one data path. The controller performs a readahead operation in response to a read request input from an external device, determines a data attribute regarding readahead data, obtained by the readahead operation, based on a time difference between reception of the read request and completion of the readahead operation, and stores the readahead data in one of the plural storage regions based on the data attribute.

A system includes a first memory device having a region allocated as a first persistent memory region (PMR) having a first set of pages, a second memory device comprising a non-volatile memory device having a region allocated as a second PMR region having a second set of pages, and at least one processing device, operatively coupled to the first memory device and the second memory device, to implement a PMR mechanism to cause the second PMR region to be accessible through the first PMR region.

A memory controller includes a command queue, a memory interface queue, at least one storage queue, and a replay control circuit. The command queue has a first input for receiving memory access commands. The memory interface queue receives commands selected from the command queue and couples to a heterogeneous memory channel which is coupled to at least one non-volatile storage class memory (SCM) module. The at least one storage queue stores memory access commands that are placed in the memory interface queue. The replay control circuit detects that an error has occurred requiring a recovery sequence, and in response to the error, initiates the recovery sequence. In the recovery sequence, the replay control circuit transmits selected memory access commands from the at least one storage queue by grouping non-volatile read commands together separately from all pending volatile reads, volatile writes, and non-volatile writes.

A memory system includes a controller, a buffer, and a nonvolatile memory including a plurality of blocks, wherein each of the blocks includes a plurality of pages and each of the pages includes a plurality of unit data portions. The controller is configured to carry out garbage collection by reading data from one or more pages of a target block of the garbage collection and selectively copying valid unit data portions included in the read data to another block, count a number of invalid unit data portions included in the read data, and accept, in the buffer, unit data portions from a host as write data, up to a number determined based on the counted number, during the garbage collection.

Embodiments of three-dimensional (3D) memory devices with a 3D NAND memory array having a plurality of pages, an on-die cache coupled to the memory array on a same chip and configured to cache a plurality of batches of program data between a host and the memory array, the on-die cache having SRAM cells, and a controller coupled to the on-die cache on the same chip. The controller is configured to check a status of an (N−2).sup.th batch of program data, N being an integer equal to or greater than 2, program an (N−1).sup.th batch of program data into respective pages in the 3D NAND memory array, and cache an N.sup.th batch of program data in respective space in the on-die cache as a backup copy of the N.sup.th batch of program data.

Apparatus and methods are disclosed, including maintaining a first group of tagged data from a host device at contiguous physical locations on a group of non-volatile memory cells of a storage system during system management operations on the group of non-volatile memory cells including the first group of tagged data while the first group of tagged data remains stored on the storage system and prioritizing, in the storage system, commands associated with the first group of tagged data.

Aspects relate to Input/Output (IO) Memory Management Units (MMUs) that include hardware structures for implementing virtualization. Some implementations allow guests to setup and maintain device IO tables within memory regions to which those guests have been given permissions by a hypervisor. Some implementations provide hardware page table walking capability within the IOMMU, while other implementations provide static tables. Such static tables may be maintained by a hypervisor on behalf of guests. Some implementations reduce a frequency of interrupts or invocation of hypervisor by allowing transactions to be setup by guests without hypervisor involvement within their assigned device IO regions. Devices may communicate with IOMMU to setup the requested memory transaction, and completion thereof may be signaled to the guest without hypervisor involvement. Various other aspects will be evident from the disclosure.

A storage system, a file storage and reading method, and a terminal device are provided. A storage system including a UFS is used as an example. The storage system configures different medium forms of the UFS, for example, configures persistent storage space of the UFS including SLC and TLC medium forms, to implement hybrid medium multi-disk storage. Based on the storage system, a hot file related to an application running rate is preferentially selected and stored in an SLC storage area of the UFS, and files on a mapped multi-disk are mounted on a same directory of a file system, so that files can be migrated between the SLC storage area and a TLC storage area without user perception, to improve performance of the storage system.

A method includes accessing a first memory component of a memory sub-system via a first interface, accessing a second memory component of the memory sub-system via a second interface, and transferring data between the first memory component and the second memory component via the first interface. The method further includes initially writing data in the first memory component via a first address window and accessing data in the second memory component via a second address window in response to caching the data in first memory component to the second memory component, wherein caching the data in the first memory component to the second component includes changing an address for the data from the first address window to the second address window.