A memory module comprises a volatile memory subsystem including DRAM, a non-volatile memory subsystem including Flash memory, and a module control device. The Flash memory includes main Flash providing a main Flash memory space and scratch Flash providing a scratch Flash memory space. The module control device is configured to receive a request from the memory controller to move one or more segments of data in a first Flash block in the main Flash to the DRAM and to, for each respective segment of data: select a respective set of pages in the DRAM; transfer respective data stored in the respective set of pages from the DRAM to a corresponding segment in the scratch Flash; and transfer the respective segment of data to the respective set of pages in the DRAM. Thus, data can be moved segment by segment between the DRAM and the Flash memory.

A processing device in a host system monitors a data temperature of a plurality of memory pages stored in a host-addressable region of a cache memory component operatively coupled with the host system. The processing device determines that a first memory page of the plurality of memory pages satisfies a first threshold criterion pertaining to the data temperature of the first memory page and sends a first migration command indicating the first memory page to a direct memory access (DMA) engine executing on a memory-mapped storage component operatively coupled with the cache memory component and with the memory-mapped storage component via a peripheral component interconnect express (PCIe) bus. The first migration command causes the DMA engine to initiate a first DMA transfer of the first memory page from the cache memory component to a host-addressable region of the memory-mapped storage component.

A system and method for presenting a sales demonstration using a user interface of a pool/spa controller is provided. A first device includes a system controller user interface and sends data to a second device. The second device processes the data to present a media presentation which exhibits systems, associated features, and their ability to be controlled via a controller. A user can control pool and/or spa equipment using the first device, and the user's input can guide a presentation on the second device, which demonstrates corresponding features of such equipment. As such, the natural connections among a user, a controller, and an associated feature are demonstrated in a sales-effective manner. Additionally, the first device can present a user with a simulation of a control system interface to allow for effective sales of products.

In some examples, performance counters for computer memory may include ascertaining a request associated with a memory address range of computer memory. The memory address range may be assigned to a specified performance tier of a plurality of specified performance tiers. A performance value associated with a performance attribute of the memory address range may be ascertained, and based on the ascertained performance value, a weight value may be determined. Based on the ascertained request and the determined weight value, a count value associated with a counter associated with the memory address range may be incremented. Based on an analysis of the count value associated with the counter, a determination may be made as to whether the memory address range is to be assigned to a different specified performance tier of the plurality of specified performance tiers. Based on a determination that the memory address range is to be assigned to the different specified performance tier, the memory address range may be assigned to the specified different performance tier.

A control apparatus includes a processor configured to execute a procedure including: receiving, from a processing device, a reading request to read a first data piece among a plurality of data pieces included in a data set, the processing device executing a given process on each of the data pieces; reading the first data piece from a first storage tier among a plurality of hierarchical storage tiers having respective different reading capabilities; transmitting the read first data piece to the processing device in response to the reading request; measuring a processing time that the processing device takes to execute the given process; determine a storage tier that is to store the first data piece among the hierarchical storage tiers based on the reading capabilities and the measured processing time; and migrating the first data piece from the first storage tier to the determined storage tier.

A computing system has a first processing device (e.g., CPU, FPGA, or GPU) and memory regions (e.g., in a DRAM device) used by the processing device during normal operation. In one approach, the computing system is configured to: collect data associated with operation of an autonomous vehicle; monitor, by a first processing device, the collected data; and based on the monitoring, determine that an event on the autonomous vehicle has occurred. The computing system is further configured to, in response to determining that the event has occurred, initiate a transfer of data controlled by a second processing device, the transfer including copying data stored in volatile memory of the autonomous vehicle to non-volatile memory of the autonomous vehicle, wherein the second processing device controls copying of the data independently of the first processing device. The computing system is also further configured to, in response to determining that the event has occurred, reduce or terminate power to the first processing device.

A solid state drive (SSD) device includes: non-volatile memory, and volatile memory associated with an SSD device controller. In response to determining that the SSD device is to transition to a power saving mode, information is transferred from the volatile memory to a host memory of a host computer via a communication interface, and the at least some of the volatile memory is transitioned to an OFF state. In response to determining that the SSD device is to transition from the power saving mode to a normal operating mode, the at least some of the volatile memory of the SSD device is transitioned to an ON state in which the at least some of the volatile memory is capable of retaining data, and the information from the host memory is transferred to the volatile memory of the SSD device via the communication interface.

Aspects relate to Input/Output (IO) Memory Management Units (MMUs) that include hardware structures for implementing virtualization. Some implementations allow guests to setup and maintain device IO tables within memory regions to which those guests have been given permissions by a hypervisor. Some implementations provide hardware page table walking capability within the IOMMU, while other implementations provide static tables. Such static tables may be maintained by a hypervisor on behalf of guests. Some implementations reduce a frequency of interrupts or invocation of hypervisor by allowing transactions to be setup by guests without hypervisor involvement within their assigned device IO regions. Devices may communicate with IOMMU to setup the requested memory transaction, and completion thereof may be signaled to the guest without hypervisor involvement. Various other aspects will be evident from the disclosure.

A multi-tiered data storage system for building management system (BMS) data includes a plurality of data stores including a first data store and a second data store. The system further includes a data access router configured to provide a consistent endpoint for the BMS data to an application that provides or consumes the BMS data regardless of whether the BMS data is stored in the second data store or the first data store, obtain a requested data object of the BMS data from the second data store in response to a determination that the requested data object is available in the second data store, and obtain the requested data object from the first data store in response to a determination that the requested data object is not available in the second data store.

The present disclosure includes apparatuses and methods related to dual speed memory. A memory module can include a number of memory devices that coupled to a host via a number of first ports and coupled to a controller via a number of second ports. The memory module can be configured to transfer data on the first number of ports at a first clock speed and transfer data on the second number of ports at a second clock speed. An example apparatus can include a first number of memory devices coupled to a host via a first number of ports, and a second number of memory devices coupled to the first number of memory device via a second number of ports, wherein the first number of memory devices are configured to transfer data between the first number of memory devices and the host at a first clock speed via the first number of ports and the second number of memory devices are configured to transfer data between the first number of memory devices and the second number of memory devices at a second clock speed via the second number of ports.