Approaches for fabricating RRAM stacks with reduced forming voltage, and the resulting structures and devices, are described. In an example, a resistive random access memory (RRAM) device includes a conductive interconnect in an inter-layer dielectric (ILD) layer above a substrate. An RRAM element is on the conductive interconnect, the RRAM element including a first electrode layer on the uppermost surface of the conductive interconnect. A resistance switching layer is on the first electrode layer, the resistance switching layer including a first metal oxide material layer on the first electrode layer, and a second metal oxide material layer on the first metal oxide material layer, the second metal oxide material layer including a metal species not included in the first metal oxide material layer. An oxygen exchange layer is on the second metal oxide material layer of the resistance switching layer. A second electrode layer is on the oxygen exchange layer.

A MOS integrated circuit basic unit includes: a drain semiconductor region; a lightly doped drain region; a channel semiconductor region; a source semiconductor region; a source electrode; a gate electrode; a gate dielectric layer; and a drain electrode. The drain semiconductor region is the bottom of the basic unit. The gate electrode has a ring structure, which surrounds the channel semiconductor region, the source semiconductor region and the lightly doped drain region. The upper surface of the gate electrode is aligned to the upper surface of the source semiconductor region; and a bottom surface of the gate electrode is lower than an interface of the lightly doped drain region and the drain semiconductor region. The gate dielectric layer is disposed between the gate electrode and the adjacent functional layer. The drain semiconductor region is connected to the drain electrode of the basic unit.

An integrated circuit includes a first time delay circuit, a second time delay circuit, and a master-slave flip-flop having a gated input circuit and a transmission gate. The first time delay circuit has a first input configured to receive a first clock signal and having a first output configured to generate a second clock signal. The second time delay circuit has a second input configured to receive the second clock signal and having a second output configured to generate a third clock signal. The transmission gate is configured to receive the first clock signal and the second clock signal to control a transmission state of the transmission gate. The gated input circuit is configured to have an input transmission state controlled by the third clock signal at the second output of the second time delay circuit.

The present disclosure is directed toward carbon based diodes, carbon based resistive change memory elements, resistive change memory having resistive change memory elements and carbon based diodes, methods of making carbon based diodes, methods of making resistive change memory elements having carbon based diodes, and methods of making resistive change memory having resistive change memory elements having carbons based diodes. The carbon based diodes can be any suitable type of diode that can be formed using carbon allotropes, such as semiconducting single wall carbon nanotubes (s-SWCNT), semiconducting Buckminsterfullerenes (such as C60 Buckyballs), or semiconducting graphitic layers (layered graphene). The carbon based diodes can be pn junction diodes, Schottky diodes, other any other type of diode formed using a carbon allotrope. The carbon based diodes can be placed at any level of integration in a three dimensional (3D) electronic device such as integrated with components or wiring layers.

The present disclosure is directed toward carbon based diodes, carbon based resistive change memory elements, resistive change memory having resistive change memory elements and carbon based diodes, methods of making carbon based diodes, methods of making resistive change memory elements having carbon based diodes, and methods of making resistive change memory having resistive change memory elements having carbons based diodes. The carbon based diodes can be any suitable type of diode that can be formed using carbon allotropes, such as semiconducting single wall carbon nanotubes (s-SWCNT), semiconducting Buckminsterfullerenes (such as C60 Buckyballs), or semiconducting graphitic layers (layered graphene). The carbon based diodes can be pn junction diodes, Schottky diodes, other any other type of diode formed using a carbon allotrope. The carbon based diodes can be placed at any level of integration in a three dimensional (3D) electronic device such as integrated with components or wiring layers.

The present disclosure concerns a phase-change memory manufacturing method and a phase-change memory device. The method includes forming a first insulating layer in cavities located vertically in line with strips of phase-change material, and anisotropically etching the portions of the first insulating layer located at the bottom of the cavities; and a phase-change memory device including a first insulating layer against lateral walls of cavities located vertically in line with strips of phase-change material.

The present disclosure provides a method that includes receiving a semiconductor substrate that includes an integrated circuit (IC) cell and a well tap cell surrounding the IC cell; forming first fin active regions in the well tap cell and second fin active regions in the IC cell; forming a hard mask within the well tap cell, wherein the hard mask includes openings that define first source/drain (S/D) regions on the first fin active region of the well tap cell; forming gate stacks on the second fin active regions within the IC cell and absent from the well tap cell, wherein the gate stacks define second S/D regions on the second fin active regions; epitaxially growing first S/D features in the first S/D regions using the hard mask to constrain the epitaxially growing; and forming contacts landing on the first S/D features within the well tap cell.

A semiconductor device including stacked access device and resistive memory includes a stack disposed on a base structure, the stack including an access device stack and a resistive random-access memory (ReRAM) device stack, sidewall spacers disposed along a portion of the stack, a dielectric layer disposed over the stack, the sidewall spacers and the base structure, and an interlevel dielectric disposed on the dielectric layer.

Embodiments of the disclosure provide an integrated circuit (IC) structure, including: a semiconductor base on a first portion of a raised region of an insulative layer; a first inner emitter/collector (E/C) material on a second portion of the raised region of the insulative layer, wherein the inner E/C material is directly horizontally between the semiconductor base and a sidewall of the raised region; and a first outer E/C material on a first non-raised region of the insulative layer, wherein an upper portion of the first outer E/C material is adjacent the first inner E/C material.

A functional contactor is provided. The functional contactor according to one embodiment of the present invention comprises: a conductive elastic portion having elasticity and electrically contacting one of a circuit board of an electronic device, a bracket coupled to the circuit board, and a conductor which can come into contact with the human body; a substrate made from a dielectric material and having a groove in either the upper surface or the lower surface thereof; and a functional element comprising a high dielectric material inserted into the groove and made from sintered ceramic having a higher dielectric constant than a dielectric material, a first electrode disposed on the upper surface of the substrate and electrically connected in series to the conductive elastic portion, and a second electrode disposed on the lower surface of the substrate and opposite to the first electrode.