A system and method for determining an Angle of Arrival (AOA) for frequency modulated communications. The system may include first and second antennas spaced apart from each other by a distance, and configured to receive wireless communications in the form of a modulated signal. The system may determine a phase difference between the received signals based on one or more samples of a dedicated portion of the received signals, where one or more aspects of the dedicated portion is variable.

A method and transmission system for amplifying and providing navigation signals. The system comprises a splitter circuit configured to receive a plurality of radio frequency (RF) signals oscillating at at least two different frequencies f.sub.1 and f.sub.2. The splitter circuit is further configured to split and forward the RF signals having the f.sub.1 frequency to a first bandpass filter and the RF signals having the f.sub.2 frequency to a second bandpass filter. The system further comprises a first tunable amplifier configured to receive the RF signals from the first bandpass filter. The system further comprises a second tunable amplifier configured to receive the RF signals from the second bandpass filter at substantially the same time as the first tunable amplifier's receipt of the RF signals from the first bandpass filter. The first tunable amplifier is further configured to amplify its RF signals across a first band centered around the frequency f.sub.1. The second tunable amplifier is further configured to amplify its RF signals across a second band centered around the frequency f.sub.2. The amplified RF signals are fed substantially concurrently into a mixer circuit for transmission via an RF antenna to a navigation receiver.

An apparatus is disclosed for flexible beamforming using frequency-division multiplexing. In an example aspect, an apparatus includes an antenna array and a wireless transceiver with two or more dedicated receive paths respectively coupled to two or more antenna elements of the antenna array, two or more mixers, a first combiner, a second combiner, and a switching circuit. The first combiner has a first input coupled to a first dedicated receive path and an output coupled to an input of a first mixer. The second combiner has a first input coupled to an output of the first mixer and a second input coupled to an output of a second mixer. The switching circuit is configured to selectively connect a second dedicated receive path to a second input of the first combiner or connect the second dedicated receive path to an input of the second mixer.

A frequency multiplier includes an input section having inputs to receive an input signal having an input frequency, a mixer section, and an output section magnetically coupled to the input section and generating an output signal in response to the input signal. The mixer section may be coupled to the input section by a common mode node forming a path for a common mode current to flow to the mixer section and be magnetically coupled to the common mode node. The input section may generate a signal current, and the mixer section may be magnetically coupled to the input section and be directly capacitively coupled to the input section through a capacitor in a signal current path. The mixer section may have differential inputs capacitively coupled to the input section and also be coupled to the input section through a current path. A current helper section may be coupled to the current path.

A frequency multiplier includes an input section having inputs to receive an input signal having an input frequency, a mixer section, and an output section magnetically coupled to the input section and generating an output signal in response to the input signal. The mixer section may be coupled to the input section by a common mode node forming a path for a common mode current to flow to the mixer section and be magnetically coupled to the common mode node. The input section may generate a signal current, and the mixer section may be magnetically coupled to the input section and be directly capacitively coupled to the input section through a capacitor in a signal current path. The mixer section may have differential inputs capacitively coupled to the input section and also be coupled to the input section through a current path. A current helper section may be coupled to the current path.

The present technology relates to a notch filter capable of easily obtaining a desired frequency characteristic.

In an N-path filter unit, any one of a plurality of N capacitors is selected as a signal path through which a signal passes, so that the capacitor serving as the signal path is temporally switched. A plurality of N-path filter units is cascade-connected and a capacitor is inserted to a connection point between the N-path filter units. The present technology may be applied to the notch filter which eliminates a blocker and the like, for example.

An integrated frequency quadruplet consists of a pair of balanced frequency doublers that are driven in phase quadrature using a hybrid coupler. This approach results, effectively, in a “unilateral” multiplier that presents a match to the input-driving source, irrespective of the impedance of the doubler stages. The present invention applies this architecture to implement an integrated frequency quadruplet with output frequency of 160 GHz using quasi-vertical GaAs varactors fabricated on thin silicon support membranes. The quadruplet has a balanced circuit architecture that addresses degradation issues often arising from impedance mis-matches between multiplier stages. A unique quasi-vertical diode process is used to implement the quadruplet, resulting in an integrated drop-in chip module that incorporates 18 varactors, matching networks and beamleads for mounting. The chip is tailored to fit a multiplier waveguide housing resulting in high reproducibility and consistency in manufacture and performance.

Mechanisms for interferer detection can detect interferers by detecting elevated signal amplitudes in one or more of a plurality of bins (or bands) in a frequency range between a maximum frequency (f.sub.MAX) and a minimum frequency (f.sub.MIN). To perform rapid interferer detection, the mechanisms downconvert an input signal x(t) with a local oscillator (LO) to a complex baseband signal xI(t)+jxQ(t). xI(t) and xQ(t) are then multiplied by m unique pseudorandom noise (PN) sequences (e.g., Gold sequences) gm(t) to produce m branch signals for I and m branch signals for Q. The branch signals are then low pass filtered, converted from analog to digital form, and pairwise combined by a pairwise complex combiner. Finally, a support recovery function is used to identify interferers.

A signal mixing circuit device includes a first mixer, a second mixer and a signal amplifying circuit serially connected to the first mixer; the first mixer includes an RF signal input terminal for receiving an RF signal, LO signal input terminals for sampling a first and second LO signals, a first mixed-signal output terminal for outputting a first mixed signal and a second mixed-signal output terminal for outputting a second mixed signal; the second mixer includes an input terminal connected to a capacitor, two mixed-signal output terminals respectively connected to the first and second mixed-signal output terminals of the first mixer, LO signal input terminals for inversely sampling the first and second LO signals. With the double-balance nature of the second mixer core, the noise at the LO signal input terminals of the first mixer can be cancelled. A receiver includes the signal mixing circuit device is also disclosed.

A configurable passive mixer is described herein. According to one exemplary embodiment, the passive mixer comprises a clock generator, a controller, and a plurality of passive mixer cores connected in parallel. The clock generator comprises a local oscillator drive unit for each passive mixer core. The controller varies an effective transistor size of the passive mixer by separately configuring each of the passive mixer cores to enable/disable each passive mixer core. For example, the controller may selectively enable one or more of the passive mixer cores to vary the effective transistor width of the passive mixer. As the performance requirements and/or the operating communication standard change, the controller may re-configure each passive mixer core.