The invention relates to high-frequency amplifier apparatuses suitable for generating power outputs of at least 1 kW at frequencies of at least 2 MHz. The apparatuses include two LDMOS transistors each connected by their source connection to ground. The transistors can have the same design and can be arranged in an assembly (package). The apparatus also includes a circuit board lying against a cooling plate, which can be connected to ground, and the assembly is arranged on or against the circuit board. The apparatuses have a power transformer, whose primary winding is connected to the drain connections of the transistors, and a signal transmitter. A secondary winding of the signal transmitter can be connected to the gate connections of the two transistors. Each of the gate connections can be connected to ground via at least one voltage-limiting structural element.

An operational amplifier including an input stage coupled to an input terminal, an output stage coupled to an output terminal, and a gain node between the input stage and the output stage. A bias current source is couplable to the input stage to supply a bias current thereto and a current mirror circuit mirrors the bias current toward the gain node and the output stage. A switch circuit includes a switch activatable to bring the gain node to a pre-bias voltage and a switch coupled to the output stage and switchable between a first state and a second state in which the output stage is active and non-active, respectively. A further switch circuit is coupled to the output terminal and switchable between a first state and a second state in which the output stage is coupled to the output terminal and to a reference level, respectively.

A gradient amplifier includes N working half-bridge groups. In each of the working half-bridge groups, a first working half-bridge includes a first switch and a second switch, and a second working half-bridge includes a third switch and a fourth switch. An emitter of the first switch is coupled with a collector of the second switch at a first coupling point, and an emitter of the third switch is coupled with a collector of the fourth switch at a second coupling point. A gradient coil is coupled between the first coupling point and the second coupling point in each of the working half-bridge groups, and a current flowing through the gradient coil is a sum of currents flowing through the N working half-bridge groups.

The invention relates to high-frequency amplifier apparatuses suitable for generating power outputs of at least 1 kW at frequencies of at least 2 MHz. The apparatuses include two LDMOS transistors each connected by their source connection to ground. The transistors can have the same design and can be arranged in an assembly (package). The apparatus also includes a circuit board lying flat against a metallic cooling plate and connected to the cooling plate, which can be connected to ground, and the assembly is arranged on or against the circuit board. The apparatuses have a power transformer, whose primary winding is connected to the drain connections of the transistors, and a signal transmitter. A secondary winding of the signal transmitter is connected to the gate connections of the two transistors. Each of the gate connections is connected to ground via at least one voltage-limiting structural element.

A bias circuit includes a replica circuit for an amplifier circuit using a cascode type inverter, and a generation circuit that generates a bias voltage that causes a drain voltage of an input stage transistor of the amplifier circuit to be a saturation drain voltage, based on an output voltage of the replica circuit, and supplies the generated bias voltage to a cascode element of the amplifier circuit and a cascode element of the replica circuit.

The exemplified disclosure presents a highly power efficient amplifier (e.g., front-end inverter and/or amplifier) that achieves significant current reuse (e.g., 6-time for a 3-stack embodiments) by stacking inverters and splitting the capacitor feedback network. In some embodiments, the exemplified technology facilitates N-time current reuse to substantially reduced power consumption. It is observed that the exemplified disclosure facilitates significant current-reuse operation that significantly boost gain gm while providing low noise performance without increasing power usage. In addition, the exemplified technology is implemented such that current reuse and number of transistor has a generally linear relationship and using fewer transistors as compared to known circuits of similar topology.

One embodiment describes a transimpedance amplifier (TIA) system. The system includes an inverter TIA stage interconnecting an input node and an output node and configured to invert an input signal at the input node to provide a first inverted signal component at the output node. The system also includes a noise-canceling inverter stage arranged in parallel with the inverter stage and being configured to invert the input signal to provide a second inverted signal component and to invert noise from the input node. Thus, the first and second inverted signal components constructively combine at the output node and the noise is substantially mitigated at the output node.

An operational amplifier includes an output node; an output stage, comprising a plurality of output current paths and a plurality of control nodes, wherein the plurality of control nodes are respectively coupled to the plurality of output current paths, and the plurality of output current paths are coupled to the output node and respectively coupled to a plurality of power supply sources providing different voltages; and a selecting unit, configured to couple an internal output node of the operational amplifier to one of the plurality of control nodes of the output stage.

Devices, systems and methods for clamping output voltages of op-amps while minimizing post-clamping recovery delays are described. A circuit, which controls transitions between two operating modes, may include a first comparator for comparing an output voltage with a clamping voltage and outputting a first mode signal, a second comparator for comparing an input voltage with a reference voltage and outputting a second mode signal. A first logic component may receive the mode signals, perform a logical operation, and output a logic signal. A duplex output, based on a value of the logic signal, may output a track signal and an inversely corresponding hold signal, such track and hold signals being used by an op-amp circuit to configure adjusting blocks used to control transients during mode transitions.

A driver circuit is provided. The driver circuit includes a first operational amplifier circuit, a second operational amplifier circuit, and at least one power switching circuit is provided. The first operational amplifier circuit receives a first input signal and generates a first output signal according to the first input signal. The second operational amplifier circuit receives a second input signal and generates a second output signal according to the second input signal. The at least one power switching circuit is configured to be coupled to switch a first input stage circuit to one of a first output stage circuit and a second output stage circuit, and the at least one power switching circuit is further coupled to switch a second input stage circuit to the other one of the first output stage circuit and the second output stage circuit.