The present invention discloses a signal output apparatus. Each of two output circuits includes an inverter including an input terminal and an output terminal, and a resistor coupled between the output terminal and a differential output terminal. Each of MOS capacitors is coupled between the output terminals. Under a first operation mode, two current supplying circuits are disabled. The input terminals respectively receive a high and a low state input voltages and the output terminals generate a low and a high state output voltages. The capacitances become larger than a predetermined level. Under a second operation mode, one of the current supplying circuits is enabled to output a supplying current to the differential output terminal. The input terminals receive the high state input voltage. The output terminals generate the low state output voltage. The capacitances become not larger than the predetermined level.

An integrated circuit with a power-on-reset circuit includes an inverter circuit connected between the first and second supply node, a cascode-connected series of transistors MCn, for n going from 1 to N, connected between the first supply node and the input node of the inverter, and a resistive element connected between the input node of the inverter and the second supply node. The transistors in the cascode-connected series of transistors MCn pull up the input node voltage above a trip point voltage when the voltage between the input node and the first supply node is more than a threshold of the cascode-connected series. A circuit connected between the first and second supply nodes is responsive to a POR pulse output by the inverter.

To provide a power supply switching circuit which avoids an increase in current consumption. A power supply switching circuit includes MOS transistors provided between power supply input terminals and an output terminal, which have gates connected to each other and backgates connected to each other and are connected in series.

To provide a power supply switching circuit which avoids an increase in current consumption. A power supply switching circuit includes MOS transistors provided between power supply input terminals and an output terminal, which have gates connected to each other and backgates connected to each other and are connected in series.

A semiconductor assembly includes a first FET integrated within the semiconductor assembly and comprising gate, source and drain terminals. The semiconductor assembly further includes a low voltage switching device integrated within the semiconductor assembly and being configured to electrically short a gate-source capacitance of the first FET responsive to a control signal.

A circuit for comparing a voltage with a threshold, including: first and second nodes of application of the voltage; a first branch including a first transistor series-connected with a first resistor between first and second nodes; a second branch parallel to the first branch, including second and third series-connected resistors forming a voltage dividing bridge between the first and second nodes, the midpoint of the dividing bridge being connected to a control node of the first transistor; and a third branch including a second transistor in series with a resistive and/or capacitive element, between the control node of the first transistor and the first or second node, a control node of the second transistor being connected to the junction point of the first transistor and of the first resistor.

An integrated device includes at least one MOS transistor having a plurality of cells. In each of one or more of the cells a disabling structure is provided. The disabling structure is configured to be in a non-conductive condition when the MOS transistor is switched on in response to a control voltage comprised between a threshold voltage of the MOS transistor and an intervention voltage of the disabling structure, or to be in a conductive condition otherwise. A system comprising at least one integrated device as above is also proposed. Moreover, a corresponding process for manufacturing this integrated device is proposed.

Switch circuitry including an input terminal (1), said input terminal connected to the base of a first transistor (Q1) via a first resistor R3, said first transistor being an NPN Bipolar Gate Transistor (Q1), further comprising a second resistor (R5) connected between the base of said first transistor Q1 and ground, and including an output line or terminal (3) connected to the collector of said first transistor (Q1), and wherein the emitter of said first transistor (Q1) is connected to ground (earth), said circuitry further including a second transistor (Q2), said second transistor being a PNP Bipolar Gate Transistor, wherein the collector of said second transistor (Q2) is connected via a third resistor (R8) to the base of said first transistor (Q1), and the emitter of said second transistor Q2 is connected to said input terminal (1), and wherein the emitter of said second transistor (Q2) is additionally connected to the base of said second transistor Q2 via a fourth resistor R11; and the base of said second transistor (Q2) being additionally connected to the output terminal (3) via a fifth resistor (R10) and a diode (D1).

A gate control circuit includes a first pulse generator that outputs a first pulse signal when an input signal changes from a first logical level to a second logical level, a first gate controlling portion that controls a gate voltage of a first transistor based on a first control signal when the input signal is at the second logical level, a second pulse generator that outputs a second pulse signal when the input signal changes from the second logical level to the first logical level, and a second gate controlling portion that controls the gate voltage of the first transistor based on a second control signal when the input signal is at the first logical level. The first gate controlling portion includes a first overcurrent controlling portion that controls a voltage level of the first control signal after an expiration of an output period of the first pulse signal.

The present disclosure relates generally to a switch driving circuit and power factor correction circuit having the same, and more particularly, to a technology to provide a negative offset using Zener diodes to prevent malfunctions in driving a switch. The switch driving circuit to operate a switch implemented with a Field Effect Transistor (FET) includes a first Zener diode connected to a control input end of the switch; a capacitor connected in parallel with the first Zener diode; and second and third Zener diodes for providing a negative offset to fix a voltage applied between the gate and source of the switch to a negative value.