A RFDAC comprising an array of unit-cell power amplifiers, wherein the array comprises a first plurality of unit-cell power amplifiers, a second plurality of unit-cell power amplifiers, and a third plurality of unit-cell power amplifiers; wherein the first plurality of unit-cell power amplifiers are configured to operate in accordance with a first clock; wherein the second plurality of unit-cell power amplifiers are configured to operate in accordance with a second clock; wherein the third plurality of unit-cell power amplifiers are configured to operate in accordance with the first clock or the second clock. The RFDAC also comprising a decoder configured to output the first clock and an enablement signal of the first clock for the first plurality; output the second clock and an enablement signal of the second clock for the second plurality; distinguish between the first clock and the second clock for the third plurality.

An interpolation filtering system implemented by a digital circuit is provided, it includes an interpolation filtering operation controller, a cascaded drive module, an intermediate result cache Random Access Memory (RAM), and a filter coefficient storage Read Only Memory (ROM). The intermediate result cache RAM is configured to store externally input data of the interpolation filtering system and intermediate results output by the filter operation modules. The filter coefficient storage ROM is configured to store filter coefficients required for calculation by the filter operation modules. The interpolation filtering operation controller is configured to control, under the drive of counting beats output by the cascaded drive module, the master state machine to select data of the intermediate result cache TAM or externally directly input data to be sent to the cascaded filter operation modules for accumulation operation, and to select the filter coefficients of the filter coefficient storage ROM for multiplication operation.

An interpolation filtering system implemented by a digital circuit is provided, it includes an interpolation filtering operation controller, a cascaded drive module, an intermediate result cache Random Access Memory (RAM), and a filter coefficient storage Read Only Memory (ROM). The intermediate result cache RAM is configured to store externally input data of the interpolation filtering system and intermediate results output by the filter operation modules. The filter coefficient storage ROM is configured to store filter coefficients required for calculation by the filter operation modules. The interpolation filtering operation controller is configured to control, under the drive of counting beats output by the cascaded drive module, the master state machine to select data of the intermediate result cache TAM or externally directly input data to be sent to the cascaded filter operation modules for accumulation operation, and to select the filter coefficients of the filter coefficient storage ROM for multiplication operation.

A digital-to-analog converter may include an integrator, an input network comprising a plurality of parallel taps, each member of the plurality of parallel taps comprising a respective input resistance, and control circuitry configured to selectively enable and selectively disable particular members of the plurality of parallel taps in order to program an effective input resistance of the input network to control an analog gain of the digital-to-analog converter.

A filter stage system, includes a continuous time baseband filter comprising a feedback loop that employs at least one first impedance node and at least one second impedance node, wherein the at least one first impedance node has a higher impedance than the at least one second impedance node, and wherein the at least one first impedance node provides a dominant pole and the at least one second impedance node provides a non-dominant pole, and wherein the continuous time baseband filter generates a filtered current, and a mirroring component mirrors the filtered current to an output.

A hardware-in-the-loop (HIL) simulation device is provided, which includes a processing circuit and a pulse-width modulation (PWM) signal observation circuit. The PWM signal observation circuit includes an energy storage unit and the energy storage unit is coupled to the processing circuit. A signal source transmits a PWM signal to the processing circuit and the PWM signal observation circuit, and the energy storage unit is charged when the PWM signal is at high level. The processing circuit detects the voltage of the energy storage unit when detecting the falling edge of the PWM signal so as to calculate the duty cycle of the PWM signal.

A hardware-in-the-loop (HIL) simulation device is provided, which includes a processing circuit and a pulse-width modulation (PWM) signal observation circuit. The PWM signal observation circuit includes an energy storage unit and the energy storage unit is coupled to the processing circuit. A signal source transmits a PWM signal to the processing circuit and the PWM signal observation circuit, and the energy storage unit is charged when the PWM signal is at high level. The processing circuit detects the voltage of the energy storage unit when detecting the falling edge of the PWM signal so as to calculate the duty cycle of the PWM signal.

A number of unit cells of a digital-to-analog converter (DAC) may be simultaneously activated to generate an analog signal according to a decoded digital signal. However, while many unit cells may be generally the same, there may be variations in the gains associated with each unit cell (e.g., based on the locations of the activated unit cells within a unit cell array) amounting to a gain gradient that may cause error in the analog output. As such, a fill order may be set or selected to counter such variation by activating a particular arrangement of unit cells, as opposed to simply the number of unit cells, for a given digital signal. By filling the unit cell array from different sides, spatially and/or temporally, the gain gradient associated with the unit cells may be balanced to reduce error and increase the linearity of the DAC.

A number of unit cells of a digital-to-analog converter (DAC) may be simultaneously activated to generate an analog signal according to a decoded digital signal. However, while many unit cells may be generally the same, there may be variations in the gains associated with each unit cell (e.g., based on the locations of the activated unit cells within a unit cell array) amounting to a gain gradient that may cause error in the analog output. As such, a fill order may be set or selected to counter such variation by activating a particular arrangement of unit cells, as opposed to simply the number of unit cells, for a given digital signal. By filling the unit cell array from different sides, spatially and/or temporally, the gain gradient associated with the unit cells may be balanced to reduce error and increase the linearity of the DAC.

A security device includes a physical unclonable function (PUF) cell array including PUF cells connected with word lines and bit lines; first decoder circuitry connecting a first bit line connected to a target PUF cell with a first data line and a second bit line connected with a reference PUF cell to a second data line; a digital-to-analog converter (DAC) control circuit outputting first and second digital codes; a first DAC between a power supply voltage and the first data line, the first DAC generating a first analog output in response to the first digital code; a second DAC between the power supply voltage and the second data line, the second DAC generating a second analog output in response to the second digital code; and a sense amplifier comparing the first analog output and the second analog output and outputting a comparison result.