Patent classifications
H10N52/101
Device for electric field induced local magnetization
In a technique for inducing local electric field controlled magnetization, despite the absence of magnetic components, there is provided a novel heterostructure, a semiconductor device thereof, or an array of semiconductor devices. The heterostructure includes a semiconductor substrate carrying a plurality of layers forming at least one heterojunction and hosting a two-dimensional electron gas layer when one of the layer of the plurality of layers is bounded to an interacting layer being a chiral or a biological macromolecule assembly.
Hall sensor structure
A Hall sensor structure comprising a semiconductor body of a first conductivity type, a well region of a second conductivity type extending from a top side of the semiconductor body into the semiconductor body, at least three first semiconductor contact regions of the second conductivity type, each extending from a top side of the well region into the well region, at least one second semiconductor contact region of a second conductivity type, wherein the first semiconductor contact regions are spaced apart from one another and from an edge of the well region, a metallic connection contact layer is arranged on each first semiconductor contact region, the at least one second semiconductor contact region extends along the top side of the semiconductor body at least partially around the well region.
Magnetic sensor
A magnetic sensor includes a magneto-sensitive portion (105); an excitation wiring (110) formed in a wiring region above the magneto-sensitive portion (105) through intermediation of an insulating film (12), the excitation wiring (110) including a plurality of conductor portions (1101, 1102, 1103, 1104, and 1105) arranged in in order across at least one radial direction from a center axis of the magneto-sensitive portion (105); a current flowing through the excitation wiring (110) having a current density of which an absolute value becomes zero in a vicinity of a center of the magneto-sensitive portion (105) and continuously increases toward an outer side of the magneto-sensitive portion (105); and a magnetic field generated by the current flowing through the excitation wiring (110) in a direction vertical to the surface of the magneto-sensitive portion (105).
HALL INTEGRATED SENSOR AND CORRESPONDING MANUFACTURING PROCESS
An integrated Hall sensor is provided with: a main wafer (10) of semiconductor material having a substrate (101) with a first surface (101a) and a second surface (101b), opposite to the first surface (101a) along a vertical axis (y); Hall sensor terminals (1, 2, 3, 4; 1′, 2′, 3′, 4′) arranged at least one of the first and second surfaces (101a, 101b) of the substrate (101); an isolation structure (109) in the substrate (101) defining a Hall sensor plate (103) of the integrated Hall sensor, the Hall sensor terminals being arranged in the isolation structure (109). The integrated Hall sensor moreover has a test or calibration coil integrated in the wafer (10), having a plurality of windings formed, at least in part, by metal portions (130b, 170b; 130a, 170a) arranged above the first and second surfaces (101a, 101b) of the substrate (101) and defining an inner volume (1001) entirely enclosing the Hall sensor plate (103).
Approaches for embedding spin hall MTJ devices into a logic processor and the resulting structures
Approaches for embedding spin hall MTJ devices into a logic processor, and the resulting structures, are described. In an example, a logic processor includes a logic region including fin-FET transistors disposed in a dielectric layer disposed above a substrate. The logic processor also includes a memory array including a plurality of two-transistor one magnetic tunnel junction (MTJ) spin hall electrode (2T1MTJ SHE) bit cells. The transistors of the 2T1MTJ SHE bit cells are fin-FET transistors disposed in the dielectric layer.
Magnetoelectric spin orbit logic based full adder
An apparatus is provided which comprises a full adder including magnetoelectric material and spin orbit material. In some embodiments, the adder includes: a 3-bit carry generation structure and a multi-bit sum generation structure coupled to the 3-bit carry generation structure. In some embodiments, the 3-bit carry generation structure includes at least three cells comprising magnetoelectric material and spin orbit material, wherein the 3-bit carry generation structure is to perform a minority logic operation on first, second, and third inputs to generate a carry output. In some embodiments, the multi-bit sum generation structure includes at least four cells comprising magnetoelectric material and spin orbit material, wherein the multi-bit sum generation structure is to perform a minority logic operation on the first, second, and third inputs and the carry output to generate a sum output.
Amplification using ambipolar hall effect in graphene
An amplifier includes a graphene Hall sensor (GHS). The GHS includes a graphene layer formed above a substrate, a dielectric structure formed above a channel portion of the graphene layer, and a conductive gate structure formed above at least a portion of the dielectric structure above the channel portion of the graphene layer for applying a gate voltage. The GHS also includes first and second conductive excitation contact structures coupled with corresponding first and second excitation portions of the graphene layer for applying at least one of the following to the channel portion of the graphene layer: a bias voltage; and a bias current. The GHS further includes first and second conductive sense contact structures coupled with corresponding first and second sense portions of the graphene layer. The amplifier also includes a current sense amplifier (CSA) coupled to the GHS. The CSA senses current output from the GHS.
NANOSCALE STRAIN ENGINEERING OF GRAPHENE DEVICES WITH TUNEABLE ELECTRONIC CORRELATION FOR QUANTUM VALLEYTRONICS AND SPINTRONICS
A strain engineered material including a monolayer graphene sheet comprising an array of wrinkles induced by deformations in the graphene sheet, the deformations formed by a lattice of underlying nanostructures on a substrate. The lattice of nanostructures comprises rows of the nanostructures and each of the wrinkles comprise a ridge aligned on top of a different one of the rows and along an alignment direction defined by the rows. The deformations pattern a strain distribution in the graphene sheet that induces a periodically varying pseudo magnetic field distribution ranging between a positive value and a negative values, The periodically varying pseudo magnetic field distribution has field magnitude minima located parallel to and between the ridges and field magnitude maxima located near to and parallel to each of the ridges and can be designed for various valleytronic and spintronic device applications.
POWER SEMICONDUCTOR MODULE HAVING A CURRENT SENSOR MODULE FIXED WITH POTTING MATERIAL
Described is a power semiconductor module that includes: a frame made of an electrically insulative material; a first substrate seated in the frame; a plurality of power semiconductor dies attached to the first substrate; a plurality of signal pins attached to the first substrate and electrically connected to the power semiconductor dies; a busbar extending from the first substrate through a side face of the frame; a current sensor module seated in a receptacle of the frame in sensing proximity of the busbar, the current sensor module including a current sensor attached to a circuit board; and a potting material fixing the current sensor module to the frame such that no air gap is present between the current sensor and the busbar. The potting material contacts the frame and the current sensor. Methods of producing the power semiconductor module are also described.
METHOD OF PROVIDING AN AIR- AND/OR MOISTURE-BARRIER COATING ON A TWO-DIMENSIONAL MATERIAL
Methods of providing an air- and/or moisture-barrier coating on at least a portion of a two-dimensional material are described. In particular, the methods provide an improved approach for providing a doped two-dimensional material, preferably graphene, on a substrate wherein at least a portion of the two-dimensional material is coated with an air- and/or moisture-barrier coating that comprises an inorganic oxide, fluoride or sulfide. Two-dimensional materials provided with an air- and/or moisture impermeable inorganic oxide, fluoride or sulfide coating and an electronic device comprising the same are also described.