A ceramic electronic component includes an element body including a first internal electrode, a second internal electrode disposed in parallel to the first internal electrode, and a dielectric interposed between the first and second internal electrodes and surrounding them, and external electrode electrically connected to ends of the internal electrodes. The element body has a bottom surface on which respective ends of the first and second internal electrodes are exposed and a top surface. The dielectric has bottom dielectric regions adjacent to the bottom surface, a top dielectric region adjacent to the top surface, and a middle height dielectric region disposed between the bottom and top dielectric region. The bottom dielectric regions have a ratio of the concentration of one or more group 14 elements to the concentration of one or more group 2 elements that is higher than that in the top dielectric region.

A multi-layer ceramic capacitor includes: a first region including a polycrystal including, as a main component, crystal grains free from intragranular pores; a second region that includes a polycrystal including, as a main component, crystal grains including intragranular pores and includes a higher content of silicon than a content of silicon in the first region; a capacitance forming unit including ceramic layers laminated along a first direction, and internal electrodes disposed between the ceramic layers; and a protective portion including a cover that covers the capacitance forming unit and constitutes a main surface facing in the first direction, a side margin constituting a side surface facing in a second direction orthogonal to the first direction, and a ridge constituting a connection portion, the connection portion connecting the main surface and the side surface to each other. The ceramic layers include the first region. The ridge includes the second region.

A multi-layer ceramic capacitor includes: a first region including a polycrystal including, as a main component, crystal grains free from intragranular pores; a second region that includes a polycrystal including, as a main component, crystal grains including intragranular pores and includes a higher content of silicon than a content of silicon in the first region; a capacitance forming unit including ceramic layers laminated along a first direction, and internal electrodes disposed between the ceramic layers; and a protective portion including a cover that covers the capacitance forming unit and constitutes a main surface facing in the first direction, a side margin constituting a side surface facing in a second direction orthogonal to the first direction, and a ridge constituting a connection portion, the connection portion connecting the main surface and the side surface to each other. The ceramic layers include the first region. The ridge includes the second region.

To provide a dielectric composition having excellent reliability. The dielectric composition contains a main component represented by a composition formula (Sr.sub.1-xCa.sub.x).sub.m(Ti.sub.1-yHf.sub.y)O.sub.3-δN.sub.δ, in which 0.15<x≤0.90, 0<y≤0.15, 0.90≤m≤1.15, 0<δ≤0.05 are satisfied.

The present invention is directed to a multilayer capacitor and a circuit board containing the multilayer capacitor. The capacitor includes a main body containing a first set of alternating dielectric layers and internal electrode layers and a second set of alternating dielectric layers and internal electrode layers. Each set contains a first internal electrode layer and a second internal electrode layer wherein each layer includes a top edge, a bottom edge opposite the top edge, and two side edges that define a main body of the layer. Each layer contains at least one lead tab extending from the top edge of the main body of the layer and at least one lead tab extending from the bottom edge of the main body of the layer wherein the lead tabs are offset from the side edges of the main body of the layer. In addition, external terminals are electrically connected to the internal electrode layers wherein the external terminals are formed on a top surface of the capacitor and a bottom surface of the capacitor opposing the top surface of the capacitor.

The present invention is directed to a multilayer capacitor and a circuit board containing the multilayer capacitor. The capacitor includes a main body containing a first set of alternating dielectric layers and internal electrode layers and a second set of alternating dielectric layers and internal electrode layers. Each set contains a first internal electrode layer and a second internal electrode layer wherein each layer includes a top edge, a bottom edge opposite the top edge, and two side edges that define a main body of the layer. Each layer contains at least one lead tab extending from the top edge of the main body of the layer and at least one lead tab extending from the bottom edge of the main body of the layer wherein the lead tabs are offset from the side edges of the main body of the layer. In addition, external terminals are electrically connected to the internal electrode layers wherein the external terminals are formed on a top surface of the capacitor and a bottom surface of the capacitor opposing the top surface of the capacitor.

A transient voltage protection device includes: an element body; a cavity portion provided in the element body; a pair of internal electrodes disposed in the element body; and a pair of external electrodes connected to the pair of internal electrodes. The pair of internal electrodes extend along a first direction and face each other in a second direction intersecting the first direction. The cavity portion includes a gap region located between the pair of internal electrodes in the second direction. A tip portion of at least one of the pair of internal electrodes is in contact with only the element body.

A package on a die having a low resistive substrate, wherein the package comprises an inductor on low-k dielectric and a capacitor on high-k dielectric. The stacked arrangement having different dielectric materials may provide an inductor having a high Q-factor while still having a high capacitance density. In addition, moving the inductor from the die to the package and fabricating the high density capacitor on the package reduces the silicon area required permitting smaller RF/analog blocks on the chip.

A package on a die having a low resistive substrate, wherein the package comprises an inductor on low-k dielectric and a capacitor on high-k dielectric. The stacked arrangement having different dielectric materials may provide an inductor having a high Q-factor while still having a high capacitance density. In addition, moving the inductor from the die to the package and fabricating the high density capacitor on the package reduces the silicon area required permitting smaller RF/analog blocks on the chip.

An element body of a multilayer capacitor has a plurality of first electrodes and a plurality of second electrodes. At least one of the first electrodes is curved such that a first main body portion is located on an outer side of a first extending portion in a first direction, and at least one of the second electrodes is curved such that a second main body portion is located on an outer side of a second extending portion in the first direction. The following expressions (1) to (6) are satisfied for lengths L0 to L4 in a second direction and distances TL1 to TL3 between main surfaces.

0.03≤L1/L0≤0.1  (1)

0.1≤L2/L0≤0.25  (2)

0.75≤L3/L0≤0.9  (3)

0.9≤L4/L0≤0.97  (4)

0≤(TL1−TL2)/TL1≤0.02  (5)

0≤(TL1−TL3)/TL1≤0.02  (6)