To provide a thin film capacitor having high flexibility. A thin film capacitor includes: a metal foil having a roughened upper surface; a dielectric film covering the upper surface of the metal foil and having an opening through which the metal foil is partly exposed; a first electrode layer contacting the metal foil through the opening; and a second electrode layer contacting the dielectric film without contacting the metal foil. The particle diameter of crystal at a non-roughened center part of the metal foil is less than 15 μm in the planar direction and less than 5 μm in the thickness direction. This can not only enhance the flexibility of the metal foil to reduce a short-circuit failure in a state where the thin film capacitor is incorporated in a multilayer substrate but also enhance positional accuracy.

A chip component includes a substrate that has a first surface and a second surface on a side opposite to the first surface, a plurality of wall portions that are formed on a side of the first surface by using a part of the substrate, that have one end portion and one other end portion, and that are formed of a plurality of pillar units, a support portion that is formed around the wall portions by using a part of the substrate and that is connected to at least one of the end portion and the other end portion of the wall portions, and a capacitor portion formed by following a surface of the wall portion, in which each of the pillar units includes a central portion and three convex portions that extend from the central portion in three mutually different directions in a plan view and in which the wall portion is formed by a connection between the convex portions of the pillar units that adjoin each other.

A capacitor integrated structure, a capacitor unit and a manufacturing process thereof are provided. The manufacturing process of capacitor units includes the steps of: forming a plurality of capacitor stacking structures on a substrate having an insulation layer thereon; performing a first cut on insulation dividers provided between the adjacent capacitor stacking structures to form a plurality of recesses that expose first conductive portion and second conductive portion of each of the capacitor stacking structures; filling a metallic material in the recesses to form a plurality of metallic dividers that are electrically connected to the first conductive portion and the second conductive portion of each of the capacitor stacking structures; performing a second cut on the metallic dividers to form a plurality of independent capacitor units; and forming metallic walls on two opposite sides of each of the capacitor units, so as to provide a capacitor unit having two end electrodes.

A capacitor includes: at least one multi-wing structure including N axes and M wings, where the N axes extend along a first direction, and the M wings are a convex structure formed by extending from side walls of the N axes toward a direction perpendicular to the first direction, a first wing of the M wings and the N axes are formed of a first conductive material, and other wings are formed of a second conductive material; a conductive structure cladding the multi-wing structure; a dielectric layer disposed between the multi-wing structure and the conductive structure to isolate the multi-wing structure from the conductive structure; a first external electrode electrically connected to some or all multi-wing structures; and a second external electrode electrically connected to the conductive structure.

A method for manufacturing a capacitive device comprising the following steps: a) providing a metallic layer, b) depositing a full-sheet aluminium layer, c) structuring pores in the aluminium layer by a full-sheet anodic etching process, subsequently to which a continuous porous alumina layer is obtained comprising a first main face and a second main face, longitudinal pores extending from the first main face to the second main face, d) forming a capacitive area at a first area of the porous alumina layer, e) forming an upper electrode over the capacitive area, f) forming a contact resumption at a second area of the porous alumina layer, g) forming a lower electrode over the contact resumption.

Three-dimensional capacitive structures may be produced by forming a capacitive stack conformally over pores in a region of porous anodic oxide. The porous anodic oxide region is provided on a stack of electrically-conductive layers including an anodization-resistant layer and an interconnection layer. In the pores there is a position having restricted diameter quite close to the pore bottom. In a first percentage of the pores in the region of anodic oxide, a functional portion of the capacitive stack is formed so as to extend into the pores no further than the restricted-diameter position. Cracks that may be present in the anodization-resistant layer have reduced effect on the properties of the capacitive structure. Increased thickness of the anodization-resistant layer can be tolerated, enabling equivalent series resistance of the overall capacitive structure to be reduced.

An MIM capacitor or an MIS capacitor in semiconductor devices is formed of a thin dielectric layer having a total film thickness less than 100-nm and including a high-dielectric-constant amorphous insulating film, high-breakdown-voltage amorphous films such as of SiO.sub.2, and high-dielectric-constant amorphous buffer films between an upper electrode and a lower electrode. The thin high-dielectric-constant amorphous insulation film is formed of a material having a property resistant to fracture although having properties of a large leakage current and a low breakdown voltage, to enhance reliability of the thin dielectric layer and to reduce the footprint thereof in the semiconductor device.

A power storage device, containing two electrodes, and a plate-like crystal structure smectite-based clay film between the electrodes.

A ceramic electronic device includes a multilayer structure in which each of dielectric layers and each of internal electrode layers are alternately stacked, wherein a main component of the dielectric layers is (Ba, Sr, Ca)(Zr, Ti)O.sub.3, wherein a Ba concentration and a Ca concentration have variation in at least one of crystal grains in the dielectric layers.

A multilayer electronic component includes a body including a plurality of internal electrodes and a dielectric layer disposed between the plurality of internal electrodes; and an external electrode disposed on the body and connected to the plurality of internal electrodes, wherein each of the plurality of internal electrodes includes a plurality of nickel layers, and a heterogeneous material layer provided between the plurality of nickel layers.