Patent classifications
H01G4/385
CAPACITANCE STRUCTURE AND MANUFACTURING METHOD THEREOF
A capacitance structure includes a substrate, a plurality of rod capacitors and an oxide layer. The rod capacitors are located on a top surface of the substrate and form a capacitor array. The oxide layer covers a top and a side of the capacitor array and a portion of the substrate. The rod capacitors extend along a first direction perpendicular to a second direction in which the top surface of the substrate extends. The oxide layer extends from the top of the capacitor array to the substrate along a third direction, and an angle is formed between the first and third directions.
CAPACITOR, IN PARTICULAR INTERMEDIATE CIRCUIT CAPACITOR FOR A MULTI-PHASE SYSTEM
A capacitor with a first voltage layer guided around the capacitor structure, so that the first voltage layer and the second planar electrode of the capacitor form an overlap region in which the first voltage layer and the second planar electrode are arranged, parallel to one another and separated from one another by a gap, on a base side of the capacitor directly one above the other, wherein the first voltage layer is arranged on an outer side of the second planar electrode, which outer side is averted from the capacitor structure).
Half bridge induction heating generator and a capacitor assembly for a half bridge induction heating generator
The present invention relates to a half bridge induction heating generator, comprising at least one power terminal (10) provided for a direct current voltage, at least one ground terminal (12), and four capacitors (C2, C3, C4, C5) forming a bridge circuit between the power terminal (10) and the ground terminal (12). The induction heating generator comprises further an induction coil (L) interconnected in the center of said bridge circuit, two semiconductor switches (Q1, Q2) connected in each case parallel to one of the both capacitors (C4, C5) on one side of the bridge circuit, and a further capacitor (CI) interconnected between the power terminal (10) and the ground terminal (12). The four capacitors (C2, C3, C4, C5) of the bridge circuit and the further capacitor (C1) are arranged inside a common housing (20), wherein said housing (20) and the capacitors (C1, C2, C3, C4, C5) form a capacitor assembly, which is a single component and mounted or mountable on and electrically connected or connectable to a printed circuit board. Further, the present invention relates to a capacitor assembly provided for said half bridge induction heating generator.
CAPACITOR FOR MULTIPLE REPLACEMENT APPLICATIONS
An apparatus suitable for use in an air-conditioning system and configured to provide a plurality of selectable capacitance values includes a plurality of capacitive devices and a pressure interrupter cover assembly. Each of the capacitive devices has a first capacitor terminal and a second capacitor terminal. The pressure interrupter cover assembly includes a deformable cover, a set of capacitor cover terminals, a common cover terminal, and a set of insulation structures. The apparatus also includes a conductor configured to electrically connect the second capacitor terminal of at least one of the capacitive devices to the common cover terminal.
Multilayer ceramic capacitor
In an embodiment, a capacitor body 11 of a multilayer ceramic capacitor 10 successively has a high-capacitance part CP1 and a low-capacitance part CP2 in the height direction, sharing one common internal electrode layer 14co among 30 internal electrode layers. The high-capacitance part CP1 includes 23 internal electrode layers 14-1 and one common internal electrode layer 14co, while the low-capacitance part CP2 includes one common internal electrode layer 14co and six internal electrode layers 14-2, where the facing distance FI2 of the seven internal electrode layers 14co and 14-2 included in the low-capacitance part CP2 is wider than the facing distance FI1 of the 24 internal electrode layers 14-1 and 14co included in the high-capacitance part CP1. The multilayer ceramic is capacitor capable of suppressing noise that may otherwise generate in a mounted state, while also reducing ESL in high-frequency ranges of several hundred MHz or higher.
MULTILAYER CERAMIC CAPACITOR
In an embodiment, a multilayer ceramic capacitor 10 is constituted in such a way that four capacitive components C1 to C4 that are connected in series are formed between a first internal electrode layer group 14 and a second internal electrode layer group 15 adjacent to it, wherein, among the four capacitive components C1 to C4, the facing area Sc1 that defines the capacitance value of the capacitive component C1 closest to the first external electrode 12 and the facing area Sc4 that defines the capacitance value of the capacitive component C4 closest to the second external electrode 13 are greater than the facing areas Sc2 and Sc3 that define the capacitance values of the two remaining capacitive components C2 and C3, respectively. The multilayer ceramic capacitor is capable of satisfying the needs for both size reduction and voltage resistance increase.
COMPOSITE CAPACITOR
A composite capacitor that includes a first capacitor and a second capacitor. Each of plural first columnar conductors and each of plural second columnar conductors have a nano-size outer diameter. The composite capacitor includes a connecting conductor layer and a reinforcement conductor. The reinforcement conductor is located between a first counter electrode layer and a second counter electrode layer of the first capacitor and the second capacitor, respectively, and is connected to each of the first counter electrode layer, the second counter electrode layer, and the connecting conductor layer. The material forming the reinforcement conductor is the same as each of the first counter electrode layer and the second counter electrode layer and is different from the material forming the connecting conductor layer.
COMPOSITE CAPACITOR
A composite capacitor that includes a plurality of capacitors and an insulating section. The plurality of capacitors are stacked on each other. The insulating section covers peripheral surfaces of the plurality of capacitors about a central axis of the plurality of capacitors, the stacking direction of the plurality of capacitors being a direction of the central axis. Each of the plurality of capacitors includes a support electrode layer, plural columnar conductors, a dielectric layer, and a counter electrode layer. Each of the plural columnar conductors has a nano-size outer diameter. The plurality of capacitors include a first capacitor and a second capacitor connected in parallel with the first capacitor.
CAPACITOR STRUCTURE, SEMICONDUCTOR STRUCTURE, AND METHOD FOR MANUFACTURING THEREOF
A capacitor structure is provided. The capacitor structure includes a substrate, a middle-of-line (MEOL) structure, and a metallization structure. The substrate has a first surface and a second surface opposite to the first surface. The MEOL structure is over the first surface of the substrate. The MEOL structure includes a capacitor, and the capacitor includes a bottom plate and a top plate over the bottom metal plate. The metallization structure is over the MEOL structure. The substrate further includes a plurality of first through vias extending from the second surface of the substrate to the bottom metal plate. The semiconductor structure including the capacitor structure and the method for manufacturing the semiconductor structure are also provided.
ELECTRONIC COMPONENT AND MANUFACTURING METHOD OF THE SAME
Disclosed herein is an electronic component that includes a substrate, a planarizing layer covering a surface of the substrate, a first conductive layer formed on the planarizing layer and having a lower electrode, a dielectric film made of a material different from that of the planarizing layer and covering the planarizing layer and first conductive layer, an upper electrode laminated on the lower electrode through the dielectric film, and a first insulating layer covering the first conductive layer, dielectric film, and upper electrode. An outer periphery of the first insulating layer directly contacts the planarizing layer without an intervention of the dielectric film.