Micro-scale devices, such as transformers and capacitors, having a floating conductive layer are disclosed. A floating conductive layer may be disposed in an insulator layer and can reduce a maximum electric field between a first planar conductor and a second planar conductor of a micro-scale passive device. Reduction of a maximum electric field between a first planar conductor and a second planar conductor can reduce undesirable effects on electrical components.

A multilayer ceramic capacitor includes a body including a dielectric layer and first and second internal electrodes disposed with the dielectric layer interposed therebetween in a stacking direction, and including a first surface and a second surface opposing each other in the stacking direction, a first through electrode penetrating the body and connected to the first internal electrode; a second through electrode penetrating the body and connected to the second internal electrode, first and second external electrodes disposed on the first surface and the second surface, respectively, and connected to the first through electrode, third and fourth external electrodes spaced apart from the first and second external electrodes and connected to the second through electrode, and an identifier disposed on the first surface or the second surface of the body, and the first and second through electrodes protrude from the first surface of the body.

According to an embodiment, a capacitor includes a conductive substrate, a conductive layer and a dielectric layer. The conductive substrate has a first main surface and a second main surface. The first main surface includes sub-regions. Each sub-region is provided with recesses or projections each having a shape extending in one direction and arranged in a width direction thereof. One or more of the sub-regions and another one or more of the sub-regions are different from each other in a length direction of the recesses or protrusions. The conductive layer covers sidewalls and bottom surfaces of the recesses or sidewalls and top surfaces of the projections. The dielectric layer is interposed between the conductive substrate and the conductive layer.

A semiconductor package includes a package substrate; a semiconductor die mounted on a top surface of the package substrate; a plurality of conductive elements disposed on a bottom surface of the package substrate; and a land-side silicon capacitor disposed on the bottom surface of the package substrate and surrounded by the plurality of conductive elements. The land-side silicon capacitor includes at least two silicon capacitor unit dies adjoined to each other with an integral scribe line region.

A three-terminal capacitor includes a main body having a cylindrical or substantially cylindrical shape extending in a first direction and including first and second inner electrodes alternately laminated together with dielectric layers interposed therebetween, a pair of first outer electrodes on two end surfaces of the main body in the first direction and electrically connected to the first inner electrodes, and a second outer electrode electrically connected to the second inner electrodes. The main body includes a projecting portion projecting in a direction perpendicular or substantially perpendicular to the first direction at a position between the pair of first outer electrodes. The second outer electrode is provided on one surface of the projecting portion viewable when viewed in the first direction.

A multilayer ceramic capacitor includes a multilayer body and outer electrodes. The multilayer body includes first and second multilayer ceramic structures and an intermediate body between the first and second multilayer ceramic structures, first to fourth connection electrodes electrically connecting first inner electrodes, second inner electrodes, third inner electrodes, and fourth inner electrodes, respectively, a first connection wire electrically connecting the first connection electrode and one of the third connection electrode and the fourth connection electrode, and a second connection wire electrically connecting the second connection electrode and the other connection electrode. A current route from the first connection electrode via the first connection wire to the one connection electrode and a current route from the second connection electrode via the second connection wire to the other connection electrode have different lengths.

An electrical device that includes: a substrate; an anodic porous oxide region above the substrate; a first capacitor electrode region arranged in the anodic porous oxide region, extending in the anodic porous oxide region, the first capacitor electrode region having a first wall perpendicular to the top surface; a second capacitor electrode region arranged in the anodic porous oxide region, extending in the anodic porous oxide region, the second capacitor electrode region having a second wall perpendicular to the top surface and facing the first wall of the first capacitor electrode region, the first wall of the first capacitor electrode region and the second wall of the second capacitor electrode region being separated by a dielectric portion comprising a part of the anodic porous oxide region.

A capacitor provides a plurality of selectable capacitance values, by selective connection of six capacitor sections of a capacitive element each having a capacitance value. The capacitor sections are provided in a plurality of wound cylindrical capacitive elements. Two vertically stacked wound cylindrical capacitance elements may each provide three capacitor sections. There may be six separately wound cylindrical capacitive elements each providing a capacitor section. The capacitor sections have a common element terminal. A pressure interrupter cover assembly is sealingly secured to the open end of case for the elements and has a deformable cover with a centrally mounted common cover terminal and a plurality of section cover terminals mounted at spaced apart locations. A conductor frangibly connects the common element terminal of the capacitor section to the common cover terminal and conductors respectively frangibly connect the capacitor section terminals to the section cover terminals. Deformation of the cover caused by failure of the capacitor element breaks at least some of the frangible connections sufficient to disconnect the capacitive element from an electric circuit in which it is connected. A cover insulation barrier mounted on the deformable cover, has a barrier cup substantially surrounding the common cover terminal and a plurality of barrier fins each extending radially outwardly from the barrier cup, and deployed between adjacent section cover terminals.

According to an embodiment, a capacitor includes a conductive substrate, a conductive layer, a dielectric layer therebetween, and first and second internal electrodes. The substrate has first and second main surfaces. One partial region of the first main surface is provided with first recesses. A region of the second surface corresponding to a combination of the one partial region and another partial region is provided with second recesses. The conductive layer covers the main surfaces and side walls and bottom surfaces of the recesses. The first internal electrode is provided on the one partial region and electrically connected to the conductive layer. The second internal electrode is provided on the another partial region and electrically connected to the substrate.

A capacitor provides a plurality of selectable capacitance values, by selective connection of six capacitor sections of a capacitive element each having a capacitance value. The capacitor sections are provided in a plurality of wound cylindrical capacitive elements. Two vertically stacked wound cylindrical capacitance elements may each provide three capacitor sections. There may be six separately wound cylindrical capacitive elements each providing a capacitor section. The capacitor sections have a common element terminal.