A semiconductor device according to the present disclosure includes an electrically conductive first electrode block, an electrically conductive submount, an insulating layer, a semiconductor element, an electrically conductive bump, and an electrically conductive second electrode block. The submount is provided in a first region of the upper surface of the first electrode block, and electrically connected to the first electrode block. The semiconductor element is provided on the submount, and has a first electrode electrically connected to the submount. The bump is provided on the upper surface of a second electrode, opposite the first electrode, of the semiconductor element, and electrically connected to the second electrode. A third region of the lower surface of the second electrode block is electrically connected to the bump via an electrically conductive metal layer. An electrically conductive metal sheet is provided between the metal layer and the bump.

A lid has a heat conductive substrate, a crystallized amorphous silicon layer and a native silicon oxide layer formed on the crystallized amorphous silicon layer. Another embodiment has a lid with a copper substrate and a native silicon oxide layer connected to the substrate by at least one intermediate layer. A method of providing a heat path through an integrated circuit package includes providing a substrate with an exterior layer of native silicon oxide and interfacing the layer of native silicon oxide with a layer of thermal interface material.

A lid has a heat conductive substrate, a crystallized amorphous silicon layer and a native silicon oxide layer formed on the crystallized amorphous silicon layer. Another embodiment has a lid with a copper substrate and a native silicon oxide layer connected to the substrate by at least one intermediate layer. A method of providing a heat path through an integrated circuit package includes providing a substrate with an exterior layer of native silicon oxide and interfacing the layer of native silicon oxide with a layer of thermal interface material.

A lens cap for a transistor outline (TO) package is provided that has an inner diameter of less than 4 mm. The lens cap includes a metal shell with a wall thickness of less than 0.2 mm and a thinned area surrounding the lens so that in the thinned area the wall thickness is reduced by at least 35%.

A lens cap for a transistor outline (TO) package is provided that has an inner diameter of less than 4 mm. The lens cap includes a metal shell with a wall thickness of less than 0.2 mm and a thinned area surrounding the lens so that in the thinned area the wall thickness is reduced by at least 35%.

A contact spring for placement in a gap between an electrical substrate opposite a lid (electrically conductive heat spreader) of an electronic device comprises a spring that both conducts heat from the substrate to the lid and electrically connects the substrate and lid. The spring comprises a flat single element configured as a plurality of polygons, providing contact points, the spring substantially lying in a plane and extending substantially in a straight line, or a spiral. The spring in an electronic device such as a flip chip ball grid array having this lid and an electrical substrate with EMI emitters: (1) provides low impedance electrical connection between the electronic circuit and lid; (2) grounds the lid to the electronic circuit; (3) minimizes EMI in the electronic circuit; (4) conducts heat from the electronic circuit to the lid; or any one or combination of the foregoing features (1)-(4).

A contact spring for placement in a gap between an electrical substrate opposite a lid (electrically conductive heat spreader) of an electronic device comprises a spring that both conducts heat from the substrate to the lid and electrically connects the substrate and lid. The spring comprises a flat single element configured as a plurality of polygons, providing contact points, the spring substantially lying in a plane and extending substantially in a straight line, or a spiral. The spring in an electronic device such as a flip chip ball grid array having this lid and an electrical substrate with EMI emitters: (1) provides low impedance electrical connection between the electronic circuit and lid; (2) grounds the lid to the electronic circuit; (3) minimizes EMI in the electronic circuit; (4) conducts heat from the electronic circuit to the lid; or any one or combination of the foregoing features (1)-(4).

A semiconductor package for mounting to a printed circuit board (PCB) includes a case comprising a ceramic base, a semiconductor die in the case, a mounting pad under the ceramic base and coupled to the semiconductor die through at least one opening in the ceramic base. The mounting pad includes at least one layer having a coefficient of thermal expansion (CTE) approximately matching a CTE of the ceramic base. The mounting pad includes at least one layer having a low-yield strength of equal to or less than 200 MPa. The mounting pad includes at least one copper layer and at least one molybdenum layer. The semiconductor package also includes a bond pad coupled to another mounting pad under the ceramic base through a conductive slug in the ceramic base.

A semiconductor package for mounting to a printed circuit board (PCB) includes a case comprising a ceramic base, a semiconductor die in the case, a mounting pad under the ceramic base and coupled to the semiconductor die through at least one opening in the ceramic base. The mounting pad includes at least one layer having a coefficient of thermal expansion (CTE) approximately matching a CTE of the ceramic base. The mounting pad includes at least one layer having a low-yield strength of equal to or less than 200 MPa. The mounting pad includes at least one copper layer and at least one molybdenum layer. The semiconductor package also includes a bond pad coupled to another mounting pad under the ceramic base through a conductive slug in the ceramic base.

A Zr-based amorphous alloy is provided; the formula of the Zr-based amorphous alloy is (Zr, Hf, Nb).sub.aCu.sub.bNi.sub.cAl.sub.dRe.sub.e, where a, b, c, d, and e are corresponding atomic percent content of elements in the Zr-based amorphous alloy, 45≦a≦65, 15≦b≦40, 0.1≦c≦15, 5≦d≦15, 0.05≦e≦5, a+b+c+d+e≦100, and Re is one of or any combination of elements La, Ce, Po, Ho, Er, Nd, Gd, Dy, Sc, Eu, Tm, Tb, Pr, Sm, Yb, and Lu, or Re is combined with Y and one of or any combination of elements La, Ce, Po, Ho, Er, Nd, Gd, Dy, Sc, Eu, Tm, Tb, Pr, Sm, Yb, and Lu.