A Zr-based amorphous alloy is provided; the formula of the Zr-based amorphous alloy is (Zr, Hf, Nb).sub.aCu.sub.bNi.sub.cAl.sub.dRe.sub.e, where a, b, c, d, and e are corresponding atomic percent content of elements in the Zr-based amorphous alloy, 45≦a≦65, 15≦b≦40, 0.1≦c≦15, 5≦d≦15, 0.05≦e≦5, a+b+c+d+e≦100, and Re is one of or any combination of elements La, Ce, Po, Ho, Er, Nd, Gd, Dy, Sc, Eu, Tm, Tb, Pr, Sm, Yb, and Lu, or Re is combined with Y and one of or any combination of elements La, Ce, Po, Ho, Er, Nd, Gd, Dy, Sc, Eu, Tm, Tb, Pr, Sm, Yb, and Lu.

A housing for a power semiconductor module arrangement includes sidewalls and a lid. The lid includes a first layer of a first material having a plurality of openings, and second layer of a second material that is different from the first material. The second layer completely covers a bottom surface of the first layer. The second layer includes a plurality of protrusions, each protrusion extending into a different one of the plurality of openings of the first layer such that each of the plurality of openings is completely covered by one of the protrusions.

A frame lid for use with a semiconductor package is disclosed. First, a mask is applied to a top surface of the lid and over a central area of the top surface to define a peripheral area. Next, a seal ring is formed by metallizing the peripheral area and the sidewall of the plate. The mask can then be removed obtain the frame lid. Next, a solder preform can be attached to the seal ring. This reduces pullback and shrinkage of the metallized layer, while lowering the manufacturing cost and process times.

A frame lid for use with a semiconductor package is disclosed. First, a mask is applied to a top surface of the lid and over a central area of the top surface to define a peripheral area. Next, a seal ring is formed by metallizing the peripheral area and the sidewall of the plate. The mask can then be removed obtain the frame lid. Next, a solder preform can be attached to the seal ring. This reduces pullback and shrinkage of the metallized layer, while lowering the manufacturing cost and process times.

The present disclosure provides a semiconductor package structure and a method of manufacturing the same. The semiconductor package structure includes a substrate, a first electronic component, an interlayer, a third electronic component and an encapsulant. The first electronic component is disposed on the substrate. The first electronic component has an upper surface and a lateral surface and a first edge between the upper surface and the lateral surface. The interlayer is on the upper surface of the first electronic component. The third electronic component is attached to the upper surface of the first electronic component via the interlayer. The encapsulant encapsulates the first electronic component and the interlayer. The interlayer does not contact the lateral surface of the first electronic component.

The method of manufacturing a semiconductor device includes receiving a substrate. The substrate comprises at least one chip region and at least one scribe line next to the chip region, and each chip region comprises an active region. The method further includes disposing a buffer layer at least covering the scribe line, disposing a dielectric layer including an opening over each chip region, and disposing a bump material to the opening of the dielectric layer and electrically connecting to the active region. The method further includes forming a mold over the substrate, covering the buffer layer and cutting the substrate along the scribe line. Furthermore, the buffer layer includes an elastic modulus less than that of the mold, or the buffer layer includes a coefficient of thermal expansion less than that of the mold.

The method of manufacturing a semiconductor device includes receiving a substrate. The substrate comprises at least one chip region and at least one scribe line next to the chip region, and each chip region comprises an active region. The method further includes disposing a buffer layer at least covering the scribe line, disposing a dielectric layer including an opening over each chip region, and disposing a bump material to the opening of the dielectric layer and electrically connecting to the active region. The method further includes forming a mold over the substrate, covering the buffer layer and cutting the substrate along the scribe line. Furthermore, the buffer layer includes an elastic modulus less than that of the mold, or the buffer layer includes a coefficient of thermal expansion less than that of the mold.

An electronic device comprises a carrier, a leadframe, a package body and a plurality of electronic components. The carrier has an open top surface, a closed bottom surface and sidewalls extending between the closed bottom surface and the open top surface. The carrier has a circular cavity in its open top surface extending toward the closed bottom surface. The carrier includes a leadframe including a die pad and a plurality of leads. The leads are physically isolated from the die pad by at least one gap. The package body partially encapsulates the leadframe such that a portion of an upper surface of the die pad and a portion of each of the leads are exposed from the package body. The exposed portions of the leads are arranged radially along the die pad. The electronic components are disposed on the die pad.

An electronic device comprises a carrier, a leadframe, a package body and a plurality of electronic components. The carrier has an open top surface, a closed bottom surface and sidewalls extending between the closed bottom surface and the open top surface. The carrier has a circular cavity in its open top surface extending toward the closed bottom surface. The carrier includes a leadframe including a die pad and a plurality of leads. The leads are physically isolated from the die pad by at least one gap. The package body partially encapsulates the leadframe such that a portion of an upper surface of the die pad and a portion of each of the leads are exposed from the package body. The exposed portions of the leads are arranged radially along the die pad. The electronic components are disposed on the die pad.

A power semiconductor device has a metal moulded body forming a first connecting conductor, with a first main surface of the metal moulded body there is a first recess having a first base in which a first power semiconductor component is arranged which faces the first base and is connected in an electrically conductive manner. From a second main surface of the metal moulded body, a second recess has a second base and a second power semiconductor component is arranged with the first contact surface thereof associated with the second base connected in an electrically conductive manner to this base. An insulating material layer is on both main surfaces, filling and completely covering the recess, wherein the first insulating layer has an electrically conductive first via which connects a second contact surface of the first power semiconductor component in an electrically conductive manner to a first conducting surface arranged on the first insulating layer.