Embodiments of the application provide a capacitive apparatus and a method for producing the same. The capacitive apparatus includes at least one capacitor; where the at least one capacitor includes at least one first dielectric layer and at least one second dielectric layer, the first dielectric layer has a positive voltage coefficient and the second dielectric layer has a negative voltage coefficient; and/or the first dielectric layer has a positive temperature coefficient and the second dielectric layer has a negative temperature coefficient. Using a principle of positive and negative cancellation, when the at least one capacitor is regarded as a whole, a voltage coefficient and/or a temperature coefficient thereof may be zero or close to zero. Thus, when a bias voltage or a temperature of the at least one capacitor changes, a capacitance value thereof does not change or changes slightly, thereby effectively ensuring the performance of the capacitive apparatus.

In an electrical circuit arrangement, which is formed by an RC-snubber element monolithically integrated into a semiconductor substrate, a first capacitor and a resistor of the RC-snubber element are vertically formed in a semiconductor region of a first type of doping of the semiconductor substrate. At least one further capacitor is connected in series with the first capacitor. The further capacitor is integrated laterally with the first capacitor in a semiconductor region of a second type of doping, which adjoins the semiconductor region of the first type of doping, and by virtue of the different type of doping electrically insulates the further capacitor from the semiconductor region of the first type of doping. This circuit arrangement forms a low inductance RC-snubber element with high dielectric strength, which has high heat dissipation and integration density.

Disclosed are devices and methods for on-die electrostatic discharge (ESD) protection in an electronic device. Aspects disclosed include an electronic device including a protected circuit disposed within a die having a first port and a second port. A first inductor is also disposed within the die and is electrically coupled to the first port. A second inductor is also disposed within the die and electrically coupled to the second port. The first inductor and the second inductor are routed in close proximity and are configured so the first inductor is out of phase with the second inductor.

According to various aspects, a memory cell arrangement includes: a first control line and a second control line; a plurality of memory structures disposed between the first control line and the second control line, wherein each memory structure of the plurality of memory structures comprises a third control line, a first memory cell and a second memory cell; wherein, for each memory structure of the plurality of memory structures, the first memory cell and the second memory cell are coupled to each other by the third control line; wherein, for each memory structure of the plurality of memory structures, the first memory cell is coupled to the first control line and the second memory cell is coupled to the second control line.

A system-on-chip may include an inductor-capacitor oscillator monolithically integrated into the system-on-chip The inductor-capacitor oscillator may be configured to improve frequency stability and reduce noise when compared to a resistor-capacitor oscillator. Methods of making integrated oscillators may involve forming an inductor at least partially while forming a BEOL structure on a substrate. A capacitor supported on and/or embedded within the semiconductor material of the substrate may be formed before or while forming the BEOL structure. The inductor may be connected to the capacitor in parallel at least partially utilizing the BEOL structure to form an integrated inductor-capacitor oscillator.

A capacitor is disclosed, including: a semiconductor substrate including opposite upper and lower surfaces; one first trench disposed in the semiconductor substrate and formed downward from the upper surface; one second trench disposed in the substrate and corresponding to the first trench, and formed upward from the lower surface; a first conductive layer disposed above the substrate and in the first trench; a first insulating layer disposed between the substrate and the first conductive layer; a second conductive layer disposed on the substrate and in the first trench, the second conductive layer being electrically connected to the substrate; a second insulating layer disposed between the second conductive layer and the first conductive layer; a third conductive layer disposed below the substrate and in the second trench; and a third insulating layer disposed between the third conductive layer and the substrate, which is electrically connected to the first conductive layer.

An apparatus including a dielectric layer; and a set of thin-film resistors arranged in a row extending in a first direction on the dielectric layer, wherein lengths of the set of thin-film resistors in a second direction substantially orthogonal to the first direction are substantially the same, wherein the set of thin-film resistors includes a first subset of one or more thin-film resistors with respective terminals spaced apart by a first distance, and wherein the set of thin-film resistors includes a second subset of one or more thin-film resistors with respective terminals spaced apart by a second distance, the first distance being different than the second distance.

An interconnect and a method of making an interconnect between one or more features on a substrate comprises: sputtering a noble metal-copper eutectic thin film under controlled power on an oxide grown or deposited on a substrate; and forming an amorphous alloy structure from the noble metal-copper eutectic thin film in the shape of the interconnect and the interconnect comprising no grain or grain boundaries without temperature sensitive resistivity.

A distributed LC filter structure is disclosed. The distributed LC filter structure provides simultaneously a distributed inductance and a distributed capacitance in the same structure. Accordingly, discrete passive elements are eliminated and high, homogenous integration is achieved. Interconnections between the distributed inductance and the distributed capacitance are tailored to leverage a parasitic inductance of the distributed capacitance to increase the overall inductance of the distributed LC filter structure. Similarly, the interconnections are tailored to leverage a parasitic capacitance resulting from the distributed inductance to add up with the distributed capacitance augmenting the overall capacitance of the structure.

A symmetrical layout structure of a semiconductor device is formed on a chip. The symmetrical layout structure is performed in a (2.sup.M+1)(2.sup.M+1) array and comprises 2.sup.Mr working units and r dummy unit(s). Each working unit has 2.sup.2+M sub-working units continuously connected by a closed trace and arranged along the closed trace in the array, wherein M is a positive integer, and r is zero or a positive integer. Each closed trace forms a parallelogram that is symmetrical to a diagonal path of the array. The working unit can be a current cell. According to the layout structure, all parallelograms have the same centroid, the perimeters of all parallelograms are the same, the lengths of the closed traces are the same, and the distances between all of the sub-current cells are the same. The present invention thus improves the performance of the digital-to-analog converter.