An IC structure includes first and second semiconductor fins extending along a first direction; first and second gate electrodes respectively extending across channel regions of the first and second semiconductor fins along a second direction perpendicular to the first direction; first and second source/drain contacts extending across source/drain regions of the first and second semiconductor fins, respectively; and first source/drain via over the first source/drain contact, wherein a width of the second source/drain contact measured along the first direction is greater than a diameter of the first source/drain via.

Semiconductor structure and a method for fabricating the semiconductor structure are provided. The semiconductor structure includes a substrate, a doped source layer formed in the substrate; a channel pillar formed on the doped source layer; a gate structure formed on the sidewall surface of the channel pillar; a first contact layer, having a first thickness and formed at the surface of the doped source layer; and a second contact layer having a second thickness and formed on the top surface of the channel pillar. The first thickness is greater than the second thickness.

A method includes doping a substrate with a dopant to form a first well region of a first core circuit and a second well region of a second core circuit; forming first and second semiconductor fins respectively over the first and second well regions and extending along a direction; forming a first gate stack across the first semiconductor fin and a second gate stack across the second semiconductor fin; forming a first source/drain adjoining the first semiconductor fin and a second source/drain adjoining the second semiconductor fin; and forming a first contact over the first source/drain and having a first width measured along the direction and a second contact over the second source/drain and having a second width measured along the direction, wherein the second width of the second contact is greater than the first width of the first contact.

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; and a die embedded in the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts and the second conductive contacts are electrically coupled to conductive pathways in the package substrate.

A method of forming a nanostructure comprises forming a directed self-assembly of nucleic acid structures on a patterned substrate. The patterned substrate comprises multiple regions. Each of the regions on the patterned substrate is specifically tailored for adsorption of specific nucleic acid structure in the directed self-assembly.

Provided is a semiconductor-manufacturing apparatus that forms a plated film having a highly homogeneous thickness on a target surface of a semiconductor wafer through electroless plating. A semiconductor-manufacturing apparatus forms plated films on target surfaces of a plurality of wafers held by a carrier capable of holding the wafers. The semiconductor-manufacturing apparatus includes the following: a rectification mechanism including a rectification plate having a plurality of through-holes, the rectification mechanism being held by the carrier in such a manner that the rectification plate faces the target surface of each wafer; a bath in which a chemical solution for forming each plated film is stored, and in which the carrier, holding the plurality of wafers and the rectification mechanism, is immersed in the chemical solution; and a driver configured to shake the carrier as immersed in the bath with a relative positional relationship between each wafer and the through-holes kept constant.

An epitaxial substrate for semiconductor elements is provided which suppresses the occurrence of current collapse. The epitaxial substrate for the semiconductor elements includes: a semi-insulating free-standing substrate formed of GaN doped with Zn; a buffer layer adjacent to the free-standing substrate; a channel layer adjacent to the buffer layer; and a barrier layer provided on an opposite side of the buffer layer with the channel layer therebetween, wherein the buffer layer is a diffusion suppressing layer formed of Al.sub.pGa.sub.1-pN (0.7p1) and suppresses diffusion of Zn from the free-standing substrate into the channel layer.

Disclosed is an ESD protection device, comprising: a semiconductor substrate; a semiconductor buried layer located in the semiconductor substrate; an epitaxial semiconductor layer located on the semiconductor substrate and comprising a first doped region and a second doped region, wherein the semiconductor substrate and the first doped region are of a first doping type, the semiconductor buried layer, the epitaxial semiconductor layer and the second doped region are of a second doping type, the first doping type and the second doping type are opposite to each other, and the first doped region forms a plurality of interfaces with the epitaxial semiconductor layer. The disclosure improves protection performance and maximum current bearing capacity without increasing parasitic capacitance of the ESD protection device.

Disclosed are structures and methods related to metallization of a gallium arsenide (GaAs) layer. In some embodiments, a tantalum nitride (TaN) layer can be formed on a doped GaAs layer, and a metal layer can be formed on the TaN layer. Such a structure can be included in a Schottky diode. In some embodiments, such a Schottky diode can be fabricated utilizing heterojunction bipolar transistor (HBT) processes.

The present invention is in the field of spintronics, and relates to a highly efficient spin filter device, such as a spin-polarizer or a spin valve, and a method for fabrication thereof.