The present invention discloses a power converter controller with short-circuit protection employing a short-circuit protection increasing slope threshold no higher than an over-current protection increasing slope threshold to detect a short-circuit abnormality in advance through a current sensing pin while any semiconductor component suffering from abnormal voltage or over-current, thereby preventing the semiconductor components from damage.

A dual-switch flyback converter in which the output current, in operating regions where a constant output current is required, can be regulated from the primary side. The output current is regulated constantly regardless of the input and output voltages by compensating the peak current in the primary winding with the average current in the clamping diode, or the conduction duration of the clamping diode.

An apparatus for controlling a power converter includes an analog-to-digital converter to generate a digital representation of a voltage sense signal indicative of an input voltage of the power converter. The apparatus includes a first comparison circuit to generate a first comparison signal using a current sense signal indicative of a current through a primary-side switch of the power converter. The apparatus includes a gate driver to provide a gate drive signal to the primary-side switch based on a control signal, and a digital controller. The digital controller is configured to produce a time scalar value using the digital representation of the voltage sense signal, produce a timing signal using the control signal and the first comparison signal, scale the timing signal using the time scalar value, and adjust a timing of the control signal to limit a peak current through the primary-side switch based on the scaled timing signal.

In an example, a system comprises a boost power factor correction (PFC) converter including a thermistor, an inductor, and a transistor coupled to a common node. The system also comprises a PFC controller coupled to the common node. The PFC controller includes a comparator coupled to a threshold voltage source and to a non-control terminal of the transistor; a first flip-flop coupled to the comparator and to a control terminal of the transistor; a zero current detector coupled to the inductor; a timer coupled to the comparator and to the zero current detector; a second flip-flop coupled to the timer and to the control terminal of the transistor; an AND gate coupled to the first and second flip-flops; a third flip-flop coupled to the second flip-flop and to the control terminal of the transistor; and a fourth flip-flop coupled to the AND gate and to the control terminal of the transistor.

A DC-DC converter includes a high-side switch coupled between a first power supply and an output terminal, a low-side switch coupled between a second power supply and the output terminal, an inductor coupled to the output terminal, and a reverse current monitoring circuit that determines that a reverse current from the inductor to the output terminal occurs when the output terminal becomes a high voltage during a state in which the high-side switch and the low-side switch are in a dead time.

The power supply apparatus of a synchronous rectification systems includes a current detection unit configured to detect a current for charging a secondary-side smoothing element, and a driving unit configured to drive a rectification unit based on a detection result by the current detection unit.

A system for turning off a synchronous rectifier (SR) based on a primary switch (PS) turn-on detection in a flyback converter having a primary-side and a secondary-side is disclosed. The system comprises the PS on the primary-side, the SR on the secondary-side, a spike detector, and a SR controller. The SR is configured to produce a drain-to-source voltage (V.sub.DS). The spike detector is in signal communication with an output capacitor (C.sub.out) on the secondary-side and the spike detector is configured to detect a voltage spike of an output voltage (V.sub.Out) across the C.sub.out that is indicative of the PS being turned-on. The SR controller is in signal communication with the SR and the spike detector and the SR controller is configured to turn-off the SR based on the spike detector detecting the voltage spike of the V.sub.Out.

A current estimation circuit is configured to estimate current within a power switch, e.g., within a switching voltage converter, using a voltage measured across its load terminals and its on-state resistance. Ringing and other transient anomalies associated with a turn-on transition of the power switch are neglected by ignoring the measured voltage across the power switch for a blanking interval after the transition. During the remainder of the conduction interval of the power switch, the measured voltage is sampled to provide first and second samples. Also during this interval, a slope of the measured voltage is estimated and tracked. The estimated slope and the first and second samples are combined to produce an estimate of the current for the entire conduction interval of the power switch, including the blanked interval. The estimated slope is used to correct for inaccuracy introduced by not using measured voltage during the blanking interval.

An automotive vehicle includes an electric machine, a traction battery, and a power converter. The power converter transfers power between the electric machine and traction battery. The power convert includes a switch that defines a portion of a phase leg, a gate driver circuit that provides provide power to a gate of the switch, and a clamping circuit. The clamping circuit includes a clamping switch that, responsive to the gate driver circuit being de-energized and a voltage of the gate exceeding a predetermined threshold value, conducts current from the gate to dissipate the voltage and clamp the gate to an emitter of the switch.

A device is configured to detect a zero voltage switching (ZVS) circuit output that includes a hard switching signal. The hard switching signal includes a false signal and a spike signal. Thereafter, the device generates digital pulse signals that correspond to the false signal and the spike signal. Accordingly, the device filters the generated digital pulse signal that corresponds to the false signal, and uses the digital pulse signal that corresponds to the spike signal for adjusting a timing of a pulse width modulation (PWM) switching cycle.