A driving circuit for driving a synchronous rectifier device. The driving circuit may include a controllable charging circuit and a slope sensing circuit. The slope sensing circuit may sense whether an abrupt rising change in a voltage drop from a sensing terminal to a reference ground terminal of the driving circuit is occurring, and provide a slope sensing signal in response to a rising edge of the abrupt rising change in the voltage drop. The controllable charging circuit may receive the slope sensing signal and provide a charging current to a supply terminal of the driving circuit in response to each rising edge of the abrupt rising change in the voltage drop.

A control circuit for controlling a synchronous rectification switch of a resonant converter, where in a switching cycle, the control circuit is configured to: delay a first time period from a first moment; control the synchronous rectification switch to be turned on when a drain-source voltage of the synchronous rectification switch reaches a first threshold after the first time period; and where the first time period is generated based on an operating state of the synchronous rectification switch in a previous switching cycle.

A current estimation circuit is configured to estimate current within a power switch, e.g., within a switching voltage converter, using a voltage measured across its load terminals and its on-state resistance. Ringing and other transient anomalies associated with a turn-on transition of the power switch are neglected by ignoring the measured voltage across the power switch for a blanking interval after the transition. During the remainder of the conduction interval of the power switch, the measured voltage is sampled to provide first and second samples. Also during this interval, a slope of the measured voltage is estimated and tracked. The estimated slope and the first and second samples are combined to produce an estimate of the current for the entire conduction interval of the power switch, including the blanked interval. The estimated slope is used to correct for inaccuracy introduced by not using measured voltage during the blanking interval.

In an example, a system comprises a boost power factor correction (PFC) converter including a thermistor, an inductor, and a transistor coupled to a common node. The system also comprises a PFC controller coupled to the common node. The PFC controller includes a comparator coupled to a threshold voltage source and to a non-control terminal of the transistor; a first flip-flop coupled to the comparator and to a control terminal of the transistor; a zero current detector coupled to the inductor; a timer coupled to the comparator and to the zero current detector; a second flip-flop coupled to the timer and to the control terminal of the transistor; an AND gate coupled to the first and second flip-flops; a third flip-flop coupled to the second flip-flop and to the control terminal of the transistor; and a fourth flip-flop coupled to the AND gate and to the control terminal of the transistor.

Systems and methods for providing peak current mode control (PCMC) for power converters. Noise immunity is improved by enhancing the signal-to-noise ratio of an inductor (or switch) current to achieve minimum duty cycle resolution and eliminate subharmonic operation that causes high input and output ripples. Current is sensed and translated to a voltage by a current sense resistor for peak current mode control scheme. A direct current (DC) offset voltage is added only during an on-time of the main switch to increase the signal-to-noise ratio. A leading-edge spike caused by turn-on of the main switch is removed by resetting a filter capacitor of a current sense circuit to zero volts after each switching cycle.

A feedback network has a feedback output terminal. A digital to analog converter has an analog output terminal. An amplifier includes an input differential pair having an inverting input terminal, a non-inverting input terminal, a first output current terminal and a second output current terminal. The inverting input terminal is coupled to the feedback output terminal, and the non-inverting input terminal is coupled to the analog output terminal. The amplifier includes a feedback differential pair having a third output current terminal, a fourth output current terminal, a first input terminal and a second input terminal. The third output current terminal is coupled to the first output current terminal, and the fourth output current terminal is coupled to the second output current terminal. The amplifier includes an amplifier output terminal coupled to the first input terminal and the second input terminal.

A method to control a high side switch of a motor drive includes sinking a current of an ON signal to communicate a turn ON of the high side switch. A first current signal, a second current signal, a third current signal, a fourth current signal and a common mode rejection signal are generated in response to the ON signal. The ON signal in a presence of common mode noise is determined by comparing the first current signal and the second current signal. A first output signal is generated in response to determining the ON signal. A drive signal is generated responsive to the first output signal to control the high side switch in response to the ON signal in presence of common mode noise that is caused by a slewing at a half-bridge node.

A switching power supply circuit has an energy storage component, a synchronous rectifier switch and a synchronous rectifier control circuit. The synchronous rectifier switch is coupled to a secondary side of the energy storage component, and the synchronous rectifier control circuit turns ON the synchronous rectifier switch based on a drain-source voltage across the synchronous rectifier switch when a primary switch is judged as turned ON. When the switching power supply circuit is not operating in a preset mode, the primary switch is judged as turned ON when the drain-source voltage remains larger than a dynamic reference voltage during a preset window time period, and when the switching power supply circuit is operating in the preset mode, the primary switch is judged as turned ON once the drain-source voltage is larger than the dynamic reference voltage.

A device [200] is configured to detect a zero voltage switching (ZVS) circuit [110] output that includes a hard switching signal. The hard switching signal [114] includes a false signal [116] and a spike signal [118]. Thereafter, the device generates digital pulse signals [312/314] that correspond to the false signal and the spike signal. Accordingly, the device filters the generated digital pulse signal that corresponds to the false signal [312], and uses the digital pulse signal [314] that corresponds to the spike signal for adjusting a timing [132] of a pulse width modulation (PWM) switching cycle [Vgs ].

An alternator and a rectifier are provided. The rectifier includes a gate driving circuit, a logic circuit, and a comparison circuit. The gate driving circuit generates a gate voltage, and a control terminal of a transistor receives the gate voltage. The gate driving circuit receives a control signal, and adjusts the gate voltage according to the control signal, so as to control a conductivity degree of the transistor. The logic circuit generates the control signal and a switch signal according to a comparison result and selects a selected voltage according to the switch signal. The comparison result is generated by comparing a sensing voltage of a first terminal of the transistor with the selected voltage.