A drive device for controlling a power switching element includes: an on-side circuit that performs an on operation of the power switching element; and an off-side circuit that performs an off operation of the power switching element. The on-side circuit or the off-side circuit includes: multiple main MOS transistors; a sense MOS transistor that define a drain current of each main MOS transistor; and a sense current control circuit that controls a drain current of the sense MOS transistor to be constant; and a switch circuit that is connected to the gate of each main MOS transistor, and controls each main MOS transistor to turn on and off so as to switch a gate current in the power switching element.

Power switch driver for driving a control terminal of a power switch to drive a load, the power switch driver having a in negative feedback circuit to control current delivered to the control terminal, the negative feedback circuit comprising:—a current output circuit comprising at least one of a current source and a current sink, the current output circuit for providing a said current of a said control terminal and configured to receive an output current control signal to control magnitude of the current provided by the current output circuit;—a terminal voltage input circuit for receiving a voltage from a said control terminal and to output an indication of said voltage;—an amplifier coupled to amplify the terminal voltage indication to generate an amplifier output; and—a reference voltage input circuit for receiving a reference voltage, comprising at least one resistor, the reference voltage input circuit coupled to a charge supply input of the amplifier, wherein—the power switch driver is configured to generate the output current control signal dependent on the amplifier output, and—the power switch driver is configured to reduce the current provided by the current output circuit responsive to an increase in the voltage received by the terminal voltage input circuit.

In a drive circuit, a rate adjuster adjusts a charging speed of a MOSFET to be faster than the charging speed of an IGBT when a drive state changer changes the first switching element from the off state to the on state first, and changes the second switching element from the off state to the on state next. The rate adjuster also adjusts a discharging speed of the MOSFET to be faster than the discharging speed of the IGBT when the drive state changer changes the MOSFET from the on state to the off state first, and changes the IGBT from the on state to the off state next.

A gate driving circuit of embodiments is provided with a first transistor which controls a gate-on voltage applied to a gate electrode of a switching device, a second transistor which controls a gate-off voltage applied to the gate electrode of the switching device, a driving logic circuit which controls turn-on/turn-off of the first and second transistors, a first power source which supplies the gate-on voltage to the gate electrode when the first transistor is turned on, a second power source which supplies the gate-off voltage to the gate electrode when the second transistor is turned on, a first gate resistance variable circuit in which a plurality of field effect transistors is connected in parallel, a second gate resistance variable circuit in which a plurality of field effect transistors is connected in parallel, and a gate resistance control circuit which controls gate voltages of a plurality of field effect transistors.

There is a problem in related-art semiconductor devices that the chip size of a semiconductor device having an active Miller clamp function cannot be reduced. According to one embodiment, a semiconductor device is configured to, when a power device is turned on or off, monitor a gate voltage Vg of the power device, set a predetermined range within a transition range, the transition range being a range within which the gate voltage Vg changes, change, when the gate voltage Vg is within the predetermined range, the gate voltage Vg of the power device by using a predetermined number of constant-current circuits, and change, when the gate voltage Vg is outside the predetermined range, the gate voltage Vg by using a larger number of constant-current circuits than the number of constant-current circuits that are used when the gate voltage Vg is within the predetermined range.

In a semiconductor device in the related art, it has been necessary to match the threshold voltage of a power element with the circuit operation of a gate driver; accordingly, it has been difficult to realize the operation of the gate driver most appropriate for the employed power element. According to one embodiment, when a power element is turned off, the semiconductor device monitors the collector voltage of the power element, and increases the number of NMOS transistors that draw out charges from the gate of the power element in a period until the collector voltage becomes lower than the pre-set determination threshold, rather than in the period after the collector voltage becomes lower than the determination threshold.

A circuit for reducing collector-emitter voltage (V.sub.CE) overshoot in an insulated gate bipolar transistor (IGBT) is provided. The circuit includes circuitry operable to generate a pulse which has a rising edge synchronized to the moment when collector or emitter current of the IGBT begins to fall during turn-off of the IGBT and a width which is a fraction of a duration of the V.sub.CE overshoot. The circuitry is further operable to combine the pulse with a control signal applied to a gate of the IGBT so as to momentarily raise the gate voltage of the IGBT during turn-off of the IGBT to above a threshold voltage of the IGBT for the duration of the pulse. A corresponding method of reducing V.sub.CE overshoot in an IGBT also is provided.

A method for operating an IGBT includes determining a maximum stationary reverse bias required for operation of the IGBT, determining a first removal charge, the removal of which at the gate of the IGBT causes an electric field strength that enables the IGBT to accept the maximum stationary reverse bias during stationary blocking, determining a second removal charge, the removal of which at the gate causes an electric field strength that leads to a dynamic avalanche, and, when the IGBT is switched off, removing from the gate during a charge removal duration a removal charge that is greater than the first removal charge and smaller than the second removal charge.

A wiring of a semiconductor switch having a gate, a collector or a drain, and an emitter or a source, includes a first arrangement having a first capacitor connected in series with a parallel connection having a first resistor and a first diode. The first arrangement is connected between the gate and the collector or drain, wherein the first diode is connected away from the gate in a flow direction. A second arrangement is connected in parallel with the first arrangement and includes a second capacitor connected in series with a parallel connection having a second resistor and a second diode, wherein the second diode lies toward the gate in the flow direction.

A semiconductor device of an embodiment includes semiconductor layer including first and second planes, and in order from the first plane's side to the second plane's side, first region of first conductivity type, second region of second conductivity type, third region of second conductivity type having second conductivity type impurity concentration higher than the second region, fourth region of first conductivity type, and fifth region of second conductivity type, and including first and second trench on the first plane's side; first gate electrode in the first trench; first gate insulating film in contact with the fifth semiconductor region; second gate electrode in the second trench; second gate insulating film; a first electrode on the first plane; second electrode on the second plane; first gate electrode pad connected to the first gate electrode; and second gate electrode pad connected to the second gate electrode.