An aspect includes an apparatus including a first amplifier; a first field effect transistor (FET) including a first source coupled to an output of the first amplifier, and a first drain for coupling to a first load; and a first gate drive circuit including an input coupled to the output of the first amplifier and an output coupled to a first gate of the first FET. Another aspect includes a method including amplifying a first audio signal using a first audio amplifier to generate a first voltage; generating a first gate voltage based on the first voltage; applying the first gate voltage to a first gate of a first field effect transistor (FET) coupled between the first audio amplifier and a first audio transducer; and applying the first voltage to a first source of the first FET.

The invention relates to an electrical circuit (1) for transmitting a useful analogue signal, which has a signal transmission path (16) with an input path (2) and an output path (3) and at least one switch (6), with which the useful signal which is carried on the input path (2) can be connected through to the output path (3) or the signal transmission path (16) can be interrupted. According to the invention, a compensation circuit (4) which substantially compensates for a distortion of the useful analogue useful signal generated by the at least one switch (6) when it is switched off (OFF) is provided, wherein the compensation circuit (4) is connected to a control terminal (G) of the at least one switch (6) and comprises at least one non-linear capacitance.

A power supply system for USB Power Delivery includes a current source drive circuit to control a power FET to regulate the supply of power along a power path. The current source drive circuit includes a cascode current source and a cascode protection circuit formed by a source follower and a feedback voltage divider. The source follower can be a transistor with its gate connected to a cascode node between upper- and lower-stage transistors of the cascode current source. The divider node of the voltage divider is connected to the gate of the lower-stage transistor. The current source drive circuit can operate within the gate-source voltage specifications of 30-volt DEPMOS devices, and can provide high output impedance to the gate of power FET and a current limit circuit during current limiting operation, without requiring an extra high-voltage mask during fabrication.

A control unit has an input with a positive and negative connectors. The control unit also includes an output and with an electronic switch. The switch has a first connector, a second connector and a control connector, and has an on-state resistance between its first and second connector that depends on a control voltage at the control connector of the switch. The first connector is connected to the connector for the positive potential of the input, the second connector is connected to the connector for the positive potential of the output, and the control connector is connected to a trigger circuit. A second controllable switch is also included with a first connector connected to the second connector of the first switch, a second connector connected to the control connector of the first switch, and a control connector connected to the connector for the negative potential of the input.

A gate driver, which drives an N-channel type transistor connected between an application terminal of an input voltage and an application terminal of a switch voltage, includes a capacitor circuit connected between an application terminal of a boot voltage higher than the switch voltage by a voltage between both ends of the boot capacitor and the application terminal of the switch voltage, and a timing control circuit that charges an input gate capacitance of the transistor with the boot voltage after precharging the same with the input voltage during turn-on transition of the transistor, and decreases capacitance value of the capacitor circuit after the turn-on transition of the transistor.

A gate driver circuit comprises an auxiliary winding, a voltage summer, an auxiliary voltage bus, a gate driver integrated circuit (IC), and a controller. The auxiliary winding is positioned adjacently to the inductor and configured to inductively couple with the inductor. The voltage summer comprises a pair of diodes coupled to the auxiliary winding and a pair of capacitors coupled to the pair of diodes. The auxiliary voltage bus is configured to receive a summed voltage from the voltage summer based on a sum of voltages stored in the pair of capacitors. The gate driver IC is configured to receive a voltage from a positive rail of the auxiliary voltage bus and to output a gate control signal to control a switching device based on the received voltage and based on a pulse signal generated by the controller.

The present disclosure provides a motor drive device. The motor drive device includes a current detection unit, a control unit and a determination unit. The current detection unit detects a current flowing through a motor coil. The control unit executes a slow attenuation mode that attenuates the current after an end of a power supply mode. The determination unit determines whether the current at a second time point while a predetermined time has elapsed from a first time point when the power supply mode is switched to a slow decay mode is below a limit value. When the determination unit determines that the current does not fall below the limit value, the control unit is configured to switch from the slow attenuation mode to a fast attenuation mode at the second time point.

A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its V.sub.GS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero V.sub.GS type, or a mix of positive-logic and zero V.sub.GS type FETs with end-cap FETs of the zero V.sub.GS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.

A device includes a charge pump configured to provide a current to a bootstrap capacitor responsive to a charge pump switch being closed. The device also includes a current limiter coupled in series between the charge pump switch and the charge pump. The current limiter is configured to receive a control signal from a controller that indicates whether the device is to operate in a first mode or in a second mode; responsive to the control signal indicating the first mode, allow a first value of current to the charge pump switch; and, responsive to the control signal indicating the second mode, limit the current to the charge pump switch to a second value. The second value is less than the first value.

Various methods and circuital arrangements for leakage reduction in MOS devices are presented. A pull-up circuit is selectively coupled to a gate of the MOS device to provide control of a voltage to the gate that is larger than a source voltage. Voltage switching circuits selectively couple different voltages to the body and/or back-gate terminals of the MOS device. During a standby mode of operation, the leakage current of the MOS device is decreased by driving the MOS device further into its subthreshold leakage region. During the standby mode, a threshold voltage of the MOS device is increased by coupling a voltage higher than the source voltage to the body and/or back-gate terminals. The MOS device can be a pass device used in low dropout regulator (LDO). During the standby mode, the LDO maintains output regulation by driving the MOS device further into its subthreshold leakage region and/or increasing the threshold voltage.