An electronic circuit includes a gate driver circuit. The gate driver circuit receives an input signal and a signal corresponding to a current through a switch, and produces, using the input signal, an output signal for controlling the switch. In response to the input signal being de-asserted, the gate driver circuit may turn the switch off at a normal turn-off rate when the current through the switch is less than an overcurrent (OC) threshold, and at an OC turn-off rate that is slower than the normal turn-off rate when the current through the switch is greater than the OC threshold.

A gate driver for a semiconductor power device and a method of driving the gate of a semiconductor power device. The current flowing through the semiconductor power device, caused by a first gate drive voltage during the present switching cycle, is sensed. Based on a second drive signal to be used in the next switching cycle, a second current is determined for that second drive signal, which are then compared to an EMC model. The EMC model defines a plurality of EMC values for respective gate drive voltages and currents conducted through the semiconductor power device. A gate drive voltage adjustment value is selected from a plurality of gate drive voltage adjustment values in the EMC model based on the predicted EMC value generated by the semiconductor power device when being driven using the second drive voltage and conducting the second current. The second gate drive voltage is adjusted using the selected gate drive voltage adjustment value for the next switching cycle.

In order to reduce the problems with sharp-edged control voltages of semiconductor switching elements, it is provided that the control terminal (6) of the semiconductor switching element (1) is connected to the output terminal (7) of the semiconductor switching element (1) via a ramp generation unit (5), and the ramp generation unit (5) flattens the sharply ascending and descending edges of the driver control voltage (V.sub.S) into the form of a ramp, in order to generate a transistor control voltage (V.sub.G) at the output of the ramp generation unit (5).

A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The second subset of the PMOS drains is different than the first subset of the PMOS drains. The first interconnect and the second interconnect are disconnected on the interconnect level. A third interconnect on the interconnect level connects a first subset of NMOS drains together of the CMOS device. A fourth interconnect on the interconnect level connects a second subset of the NMOS drains together. The second subset of the NMOS drains is different than the first subset of the NMOS drains. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, and fourth interconnects are coupled together though at least one other interconnect level.

An inverter includes an N-channel IGBT, with a freewheeling diode, coupled to a phase of an electric machine, and has a MOSFET coupling a local voltage with a gate of the IGBT and configured to transition from saturation to linear operation as a current flow direction through the diode switches from positive to negative while the IGBT initiates a current through the electric machine.

A gate control circuit includes a first pulse generator that outputs a first pulse signal when an input signal changes from a first logical level to a second logical level, a first gate controlling portion that controls a gate voltage of a first transistor based on a first control signal when the input signal is at the second logical level, a second pulse generator that outputs a second pulse signal when the input signal changes from the second logical level to the first logical level, and a second gate controlling portion that controls the gate voltage of the first transistor based on a second control signal when the input signal is at the first logical level. The first gate controlling portion includes a first overcurrent controlling portion that controls a voltage level of the first control signal after an expiration of an output period of the first pulse signal.

A load control device for controlling power delivered from an alternating-current power source to an electrical load may comprise a controllably conductive device, a control circuit, and an overcurrent protection circuit that is configured to be disabled when the controllably conductive device is non-conductive. The control circuit may be configured to control the controllably conductive device to be non-conductive at the beginning of each half-cycle of the AC power source and to render the controllably conductive device conductive at a firing time during each half-cycle (e.g., using a forward phase-control dimming technique). The overcurrent protection circuit may be configured to render the controllably conductive device non-conductive in the event of an overcurrent condition in the controllably conductive device. The overcurrent protection circuit may be disabled when the controllably conductive device is non-conductive and enabled after the firing time when the controllably conductive device is rendered conductive during each half-cycle.

A switch device includes a switching element that connects/disconnects a current path from a power supply terminal to a ground terminal via a load, and an overcurrent protection circuit that limits output current flowing in the switching element to be an overcurrent limit value or less. When an output short circuit of the load is detected, the overcurrent protection circuit decreases the overcurrent limit value to be lower as a power supply voltage is higher. In addition, the switch device preferably includes a switching element that connects/disconnects a current path from a power supply terminal to a ground terminal via a load, an intermittent control unit that intermittently drives the switching element when an abnormality is detected, and an output voltage monitoring portion that disables the intermittent control unit until an output voltage applied to the load reaches its target value.

A one-direction conduction device includes a first transistor and a driving circuit. The first transistor has a control terminal coupled to a first node, and input and output terminals respectively coupled to input and output electrode terminals of the one-direction conduction device. In the driving circuit, a switch circuit is coupled to the input electrode terminal and a second node. A second transistor has a base and a collector both coupled to a third node, and an emitter coupled to the second node. A first resistor is coupled to the third node and ground. A third transistor has a base coupled to the third node, an emitter coupled to the output electrode terminal, and a collector coupled to the first node. The second resistor is coupled between the first node and the ground. The switch circuit breaks off a reverse leakage current path of the one-direction conduction device.

A circuit for reducing collector-emitter voltage (V.sub.CE) overshoot in an insulated gate bipolar transistor (IGBT) is provided. The circuit includes circuitry operable to generate a pulse which has a rising edge synchronized to the moment when collector or emitter current of the IGBT begins to fall during turn-off of the IGBT and a width which is a fraction of a duration of the V.sub.CE overshoot. The circuitry is further operable to combine the pulse with a control signal applied to a gate of the IGBT so as to momentarily raise the gate voltage of the IGBT during turn-off of the IGBT to above a threshold voltage of the IGBT for the duration of the pulse. A corresponding method of reducing V.sub.CE overshoot in an IGBT also is provided.