Embodiments of the present disclosure provide systems and methods for realizing phase synchronization updates based on an input system reference signal SYSREF without the need to synchronously distribute the SYSREF signal on a high-speed domain. In particular, phase synchronization mechanisms of the present disclosure are based on keeping a first phase accumulator in the device clock domain and using a second phase accumulator in the final digital clock domain to asynchronously transmit phase updates to the final digital clock domain. Arrival of a new SYSREF pulse may be detected based on the counter value of the first phase accumulator, which value is asynchronously transferred and scaled to the second phase accumulator downstream. In this manner, even though the SYSREF signal itself is not synchronously transferred to the second phase accumulator, the phase updates from the SYSREF signal may be transferred downstream so that the final phase may be generated deterministically.

According to a clock generator, an oscillator outputs source oscillation clocks which are trimmed according to a trimming code. A first frequency divider generates X frequency division clocks by frequency-dividing the source oscillation clocks by a first frequency division ratio X. A trimming controller changes the trimming code within a period of the X frequency division clocks and supplies the changed trimming code to the oscillator.

A frequency generator for generating a controlled signal having a controlled frequency uses a frequency ratio generator with an input; a frequency divider for dividing the controlled frequency by a frequency ratio signal to generate a divided signal having a divided frequency; a converter for generating an excitation signal having the divided frequency, the excitation signal exciting a resonator for generating a resonance signal having a resonance frequency; a frequency phase detector of a phase difference between the divided frequency and the resonance frequency; an inner loop filter for generating the frequency ratio signal and filtering the phase difference signal to prevent instability of two frequency ratio generator loops; an output configured for providing the frequency ratio signal based on a ratio between the controlled frequency and the resonance frequency; and a controlled oscillator circuit for generating the controlled signal based on comparison of the frequency ratio with a target ratio.

A circuit for correcting phase interpolator rollover integral non-linearity errors includes a rollover detector circuit for detecting when a rollover event of a phase interpolator has occurred, and a correction circuit that adds a signed predistortion correction to a VCO clock cycle phase fraction value when the rollover detector circuit has detected the interpolator rollover event.

Disclosed is a frequency multiplication apparatus including a first frequency multiplier receiving a first signal having a first frequency and outputting a second signal having a second frequency by multiplying the first frequency by ‘n’ (‘n’ being a positive integer), a second frequency multiplier receiving the second signal and outputting a third signal having a third frequency by multiplying the second frequency by ‘m’ (‘m’ being a positive integer), and a coupler connected between an output of the first frequency multiplier and an input of the second frequency multiplier and outputting a part of the second signal.

Disclosed is a frequency multiplication apparatus including a first frequency multiplier receiving a first signal having a first frequency and outputting a second signal having a second frequency by multiplying the first frequency by ‘n’ (‘n’ being a positive integer), a second frequency multiplier receiving the second signal and outputting a third signal having a third frequency by multiplying the second frequency by ‘m’ (‘m’ being a positive integer), and a coupler connected between an output of the first frequency multiplier and an input of the second frequency multiplier and outputting a part of the second signal.

Methods and digital circuits provide frequency correction to frequency synthesizers. Dual switched-capacitor voltage detectors connected to an input signal periodically sample the voltage of the input signal, and then determine a fundamental frequency of the input signal from the output of the dual switched-capacitor voltage detectors. The sample period of the dual switched-capacitor voltage detectors is proportional to a time period between a previous pair of voltage peaks detected in the input signal, thereby eliminating harmonic components in the original signal which might otherwise cause errors in frequency estimation without causing unwanted sluggishness in the transient response of the frequency detection process. The time period between the previous pair of detected voltage peaks is used to create a decay signal that initiates a capacitor decay time for each voltage detector. Two additional digital methods of extracting the fundamental frequency as well as an envelope of an analog audio signal are also described, one utilizing a sliding sample rate, and the other utilizing a fixed sample rate.

Embodiments of the present disclosure provide an apparatus including: a phase detector for detecting a write frequency of a deserializer and a read frequency of a serializer, such that the phase detector outputs a first code sequence in response to the write frequency being greater than the read frequency, or a second code sequence at the rotator input in response to the write frequency being less than the read frequency; and a phase rotator for receiving the first code sequence or the second code sequence from the phase rotator to transmit a pacing signal having the read frequency to the deserializer, wherein the pacing signal causes the read frequency to increase or decrease based on whether the read frequency is different from the write frequency.

A control unit for generating a plurality of synchronized radio frequency (RF) output signals (RF.sub.out,i) each having a respective output frequency (f.sub.i), phase (Φ.sub.i), and amplitude (A.sub.i), including a signal comparator configured to compare a reference signal having a reference frequency (f.sub.ref) and a reference phase (Φ.sub.ref) with a feedback signal having a feedback frequency (f.sub.PLL) and a feedback phase (Φ.sub.PLL), and configured to generate an error signal representative of a difference between the reference signal and the feedback signal; and a data processing unit receiving as an input signal the error signal generated by the signal comparator, and outputting a plurality of waveform tuning signals (FTW.sub.PLL, FTW.sub.i) as a function of the error signal; wherein a plurality of waveform generators (DDS.sub.PLL, DDS.sub.i) each receiving at least one of the plurality of waveform tuning signals (FTW.sub.PLL, FTW.sub.i) output by the data processing unit, wherein each waveform generator (DDS.sub.PLL, DDS.sub.i) generates a time-dependent amplitude signal (A.sub.PLL(t), A.sub.i(t)) as a function of the received respective waveform tuning signal (FTW.sub.PLL, FTW.sub.i), wherein one predetermined amplitude signal (A.sub.PLL(t)) of the generated plurality of amplitude signals (A.sub.PLL(t), A.sub.i(t)) represents the feedback signal input to the signal comparator, and the other amplitude signals (A.sub.i(t)) represent the respective radio frequency (RF) output signals (RF.sub.out,i) to be generated, and wherein the data processing unit is configured to adjust both the waveform tuning signal (FTW.sub.PLL) corresponding to the one predetermined amplitude signal (A.sub.PLL(t)) representing the feedback signal such as to minimize the error signal, and the other waveform tuning signals (FTW.sub.i) corresponding to the other amplitude signals (A.sub.i(t)) representing the radio frequency (RF) output signals (RF.sub.out,i) based on the adjusted waveform tuning signal (FTW.sub.PLL) of the predetermined amplitude signal (A.sub.PLL(t)) representing the feedback signal.

The disclosure further describes a radio frequency (RF) power generator, an arrangement of at least two such radio frequency (RF) power generators, and a method each for generating a plurality of synchronized radio frequency (RF) output signals (RF.sub.out,i).

A fractional-N all digital phase locked loop (ADPLL) includes a randomly modulated delay having a triangular distribution to a frequency reference at an input of the fractional-n ADPLL to reduce spurious tones introduced by delta-sigma modulation of a frequency control word without requiring active control or calibration. In some embodiments, a delay line generates the randomly modulated delay based on a uniformly distributed random number with a flat spectrum that is shaped by a high pass filter.