Disclosed in some examples are systems, methods, devices, and machine-readable mediums for improved communications between a software-defined radio front-end device and a network-based computing device. Rather than packetize samples together, same bit positions from multiple ADC samples may be packetized together. If a Quality of Service (QoS) metric of the network connection between the RF front-end device and the network-based processing computing drops below a threshold, the RF front-end device may prioritize sending packets with the more significant bits over packets with less significant bits. In other examples, the RF front-end device may prioritize samples corresponding to certain data types over other data types.

A high-order converter generates a first high-order voltage V.sub.U_P and a second high-order voltage V.sub.U_N that monotonously change with mutually opposite polarities with respect to high-order m bits (1≤m<n) of the digital signal. A low-order converter generates a first low-order voltage and a second low-order voltage that monotonously change with mutually opposite polarities with respect to low-order (n−m) bits of the digital signal. A first amplifier receives one of the first and the second high-order voltages and one of the first and the second low-order voltages to output one differential analog signal. Having a configuration in common with the first amplifier, a second amplifier receives another of the first and the second high-order voltages and another of the first and the second low-order voltages to output another differential analog signal.

The audio circuit has a volume circuit structured to process a DSD signal that contains DSD data and a DSD clock. The volume circuit has a first shift register and a replacement circuit. The first shift register holds N bits of the DSD data. The replacement circuit replaces (N−M) bits (0≤M≤N) corresponding to a gain set value, out of N bits stored in the first shift register, with a mute bit string having a mark rate of substantially 50%.

An electronic circuit includes first and second channels which respectively receive first and second analog signals. The first channel includes a first digital to analog converter having an output coupled to a first input of a first sign comparator, and the second channel includes a second digital to analog converter. A switch network selectively couples, upon reception of a self-test mode signal signaling a test phase, an output of the second digital to analog converter to a second input of the first sign comparator. A ramp generation circuit supplies to the first digital to analog converter and the second digital to analog converter two identical ramps of digital codes, which are shifted by a programmable offset with respect to one another. A checking circuit issues a test status signal based on the output of the first sign comparator.

A voltage ladder is used to generate reference voltages. The voltage ladder is used by multiple digital-to-analog converters (DACs). In particular, the voltage ladder is used by multiple pulse-width modulation (PWM) DACs. Having multiple DACs utilize a common voltage ladder for their reference voltages reduces mismatched output voltages between DACs. Having multiple DACs utilize the common voltage ladder helps ensure that the reference voltages used by different DACs are not affected by process, voltage, and/or temperature variations in the reference voltages that would occur when using different voltage ladders for each DAC.

A voltage ladder is used to generate reference voltages. The voltage ladder is used by multiple digital-to-analog converters (DACs). In particular, the voltage ladder is used by multiple pulse-width modulation (PWM) DACs. Having multiple DACs utilize a common voltage ladder for their reference voltages reduces mismatched output voltages between DACs. Having multiple DACs utilize the common voltage ladder helps ensure that the reference voltages used by different DACs are not affected by process, voltage, and/or temperature variations in the reference voltages that would occur when using different voltage ladders for each DAC.

This disclosure is directed to, among other things, techniques to decouple the number of bits in a quantizer from the number of bits in the feedback digital-to-analog converter (DAC). A delta-sigma analog-to-digital converter circuit can include a first quantizer to generate an output having a first number of bits and then emulate a second quantizer, such as by using a bit truncation technique, to generate an output having a second number of bits. The feedback DAC can be coupled to receive the second number of bits, where the output of the feedback digital-to-analog converter circuit has the second number of bits. These techniques can reduce the area of the feedback DAC, e.g., 4 or 5 bits, and the techniques can achieve a higher maximum stable amplitude (MSA) because it is effectively a second order loop.

This disclosure is directed to, among other things, techniques to decouple the number of bits in a quantizer from the number of bits in the feedback digital-to-analog converter (DAC). A delta-sigma analog-to-digital converter circuit can include a first quantizer to generate an output having a first number of bits and then emulate a second quantizer, such as by using a bit truncation technique, to generate an output having a second number of bits. The feedback DAC can be coupled to receive the second number of bits, where the output of the feedback digital-to-analog converter circuit has the second number of bits. These techniques can reduce the area of the feedback DAC, e.g., 4 or 5 bits, and the techniques can achieve a higher maximum stable amplitude (MSA) because it is effectively a second order loop.

Systems and methods of implementing a mixed-signal integrated circuit includes sourcing, by a reference signal source, a plurality of analog reference signals along a shared signal communication path to a plurality of local accumulators; producing an electrical charge, at each of the plurality of local accumulators, based on each of the plurality of analog reference signals; adding or subtracting, by each of the plurality of local accumulators, the electrical charge to an energy storage device of each of the plurality of local accumulators over a predetermined period; summing along the shared communication path the electrical charge from the energy storage device of each of the plurality of local accumulators at an end of the predetermined period; and generating an output based on a sum of the electrical charge from each of the plurality of local accumulators.

A solid state imaging element according to an embodiment includes: a converter (14) that converts an analog pixel signal read out from a pixel into a bit value, successively for each of a plurality of bits, on the basis of a threshold voltage set according to a conversion history of the bit converted before a target bit; a plurality of voltage generation units (102a and 102b) that each generate a plurality of reference voltages; and a setting unit (12d) that sets the threshold voltage using the reference voltage selected from the reference voltages generated by each of the voltage generation units on the basis of a conversion result.