A solar cell including: a silicon substrate; a back electrode; a doped silicon layer; an upper electrode, wherein the upper electrode includes a plurality of three-dimensional nanostructures extending along a same direction; an electrode lead, wherein a direction of the electrode lead intersects with the direction of the plurality of three-dimensional nanostructures; wherein the three-dimensional nanostructures includes a first rectangular structure, a second rectangular structure, and a triangular prism structure; the first rectangular structure, the second rectangular structure, and the triangular prism structure are stacked, a first width of a bottom surface of the triangular prism structure is equal to a second width of a top surface of the second rectangular structure, and is greater than a third width of a top surface of the first rectangular structure, materials of the first rectangular structure and the triangular prism structure are metal.

Synaptic resistors (synstors), and their method of manufacture and integration into exemplary circuits are provided. Synstors are configured to emulate the analog signal processing, learning, and memory functions of synapses. Circuits incorporating synstors are capable of performing signal processing and learning concurrently in parallel analog mode with speed, energy efficiency, and functions superior to computers.

A complex nanostructure, which includes a first nanostructure component having at least one aperture in a side thereof; at least one second nanostructure component having a first end and a second end, wherein the first end of each of the at least one second nanostructure is inserted through a corresponding one of the at least one aperture in the first nanostructure, thereby forming at least one junction. Embodiments of the complex nanostructure include a bifurcated nanostructure transistor constructed of linear carbon nanotubes, a multiplexer constructed of a circular carbon nanotube and multiple linear carbon nanotubes, and an information unfolder constructed of linear or a combination of linear and circular carbon nanotubes. The nanotubes may optionally be decorated with genetic material such as single-strand or double-strand human DNA segments and/or may be modified by e-beam or ozone gas to add defects into the nanotubes to alter electrical/functional characteristics.

Compositions made of laminate comprised of porous carbon nanotube (CNT) are disclosed. Uses of the Compositions, particularly for reducing a formation of a load of a microorganism or of a biofilm, are also disclosed.

An electrochemical device for identifying electroactive analytes. The device includes a substrate; a sample region; a counter electrode; a reference electrode; a working electrode disposed in communication with the substrate, and the working electrode may be an electron conducting fiber. Further, the counter electrode, reference electrode, and working electrode are partially disposed in the sample region configured to be exposed to the electroactive analyte. Further yet, a counter electrode channel, reference electrode channel, and working electrode channel are disposed in the substrate configured to: accommodate each of the counter electrode, reference electrode, and working electrode, respectively, for placement in the respective channels.

Provided is a conductive material that is capable of achieving a high-electric conductivity, long-term stability under an atmospheric environment, heat and high humidity stabilities, as well as a conductive film and a solar cell using the same. The conductive material includes a mixture of carbon nanotubes (CNTs) and polystyrene sulfonic acid (PSS acid). The element ratio (S/C ratio) of sulfur (S) to carbon (C) in the mixture may be from 0.001 to 0.1 in terms of the number of atoms. CNTs and PSS acid may make up a content percentage of 10 wt % or more in the mixture. These conductive films comprised of the conductive material 6 may have a weight per unit area of the CNTs in the range from 1 mg/m.sup.2 to 10000 mg/m.sup.2. The solar cell may include the conductive film 7, wherein the film is on the surface of a semiconductor.

The present invention relates to a perovskite optoelectronic device and a manufacturing method therefor. The present invention allows manufacture of a perovskite optoelectronic device with high efficiency at a low cost, as well as improving the electrical conductivity of a carbon nanotube electrode, by laying graphene oxide over conventional carbon nanotubes and may also be applied to a flexible device.

A method of preparing a carbon nanotube monolayer film includes applying a bifunctional hydrogen-bond linker onto a substrate to prepare a surface-treated substrate, mixing carbon nanotubes having a heteroatom-containing aromatic polymer coating film with a hydrophobic solvent to obtain a composition and contacting the surface-treated substrate with the composition, and heat-treating the surface-treated substrate contacting the composition.

An integrated circuit includes a memory array that stores data, a rectifying circuit that rectifies an alternating current and generates a direct-current voltage, and a logic circuit that reads data stored in a memory. The memory array includes a first semiconductor memory element having a first semiconductor layer. The rectifying circuit includes a second semiconductor rectifying element having a second semiconductor layer. The logic circuit includes a third semiconductor logic element having a third semiconductor layer. The second semiconductor layer is a functional layer exhibiting a rectifying action and the third semiconductor layer is a channel layer of a logic element. All the first, second and third semiconductor layers, the functional layer exhibiting a rectifying action and the channel layer are formed of the same material including at least one selected from an organic semiconductor, a carbon nanotube, graphene, or fullerene.

An integrated circuit includes a two-dimensional transistor having a channel region having lateral ends in contact with first and second source/drain regions. The transistor includes a gate dielectric that is aligned with the lateral ends of the channel region. The transistor includes a gate metal on the gate dielectric. The gate metal has a relatively small lateral overlap of the first and second source/drain regions.