A multilayer ceramic capacitor includes a capacitor main body including a multilayer body including dielectric layers and internal electrode layers alternately laminated, and external electrodes each provided at one of two end surfaces of the multilayer body and connected to the internal electrode layers, and two interposers provided on both sides in a length direction of a surface of the capacitor main body. The two interposers each include a protrusion extending from one of the two interposers to another of the two interposers.

A multilayer ceramic capacitor includes a capacitor main body including a multilayer body including dielectric layers and internal electrode layers alternately laminated, and external electrodes each provided at one of two end surfaces of the multilayer body and connected to the internal electrode layers, and two interposers provided on both sides in a length direction of a surface of the capacitor main body. The two interposers each include a protrusion extending from one of the two interposers to another of the two interposers.

A multilayer capacitor includes a body including dielectric layers and internal electrodes, and external electrodes, wherein the body has first and second surfaces opposing each other in a first direction, third and fourth surfaces opposing each other in a second direction, and fifth and sixth surfaces opposing each other in a third direction perpendicular to the first and second directions. A length of a portion of the plurality of internal electrodes in the third direction in an intermediate region of the body in the first direction is greater than a length of the first surface or the second surface of the body in the third direction. The plurality of internal electrodes have a bottleneck structure between the intermediate region and at least one of the first and second surfaces, and wherein the bottleneck structure has a shape recessed into an inner portion of the body.

A multilayer ceramic electronic component includes a ceramic body including a first internal electrode and a second internal electrode disposed to be alternately stacked with a dielectric layer interposed therebetween, a first external electrode connected to the first internal electrode and including a first electrode layer, a first conductive layer, and a first metal layer, a second external electrode connected to the second internal electrode and including a second electrode layer, a second conductive layer, and a second metal layer, and a first coating layer disposed on the ceramic body, the first electrode layer and the second electrode layer, wherein the first coating layer may include an alkyl(meth)acrylate-based polymer.

A body includes dielectric films, first electrode films, and second electrode films being stacked on one another or being wound together. A first external electrode is at one end of the body and electrically connected to the first electrode films. A second external electrode is at another end of the body and electrically connected to the second electrode films. The body includes a capacitance portion in which each of the first electrode films faces a corresponding second electrode film of the second electrode films with a corresponding dielectric film of the dielectric films in between, and the capacitance portion includes spaces each between a corresponding dielectric film of the dielectric films and a corresponding first electrode film of the first electrode films or between a corresponding dielectric film of the dielectric films and a corresponding second electrode film of the second electrode films.

A body includes dielectric films, first electrode films, and second electrode films being stacked on one another or being wound together. A first external electrode is at one end of the body and electrically connected to the first electrode films. A second external electrode is at another end of the body and electrically connected to the second electrode films. The body includes a capacitance portion in which each of the first electrode films faces a corresponding second electrode film of the second electrode films with a corresponding dielectric film of the dielectric films in between, and the capacitance portion includes spaces each between a corresponding dielectric film of the dielectric films and a corresponding first electrode film of the first electrode films or between a corresponding dielectric film of the dielectric films and a corresponding second electrode film of the second electrode films.

A pre-press process includes a first step for bonding a first end portion of each of a plurality of electronic component bodies to a bonding surface of a flat plate material disposed in a jig, a second step for moving the jig relative to a surface plate, a third step for bringing a second end portions of each of the plurality of electronic component bodies into contact with the surface plate while the flat plate material is in a softened state so that the flat plate material is deformed to align respective positions of end surfaces of the second end portions, a fourth step for curing the flat plate material, and then a fifth step for moving the jig relative to the surface plate to separate from the surface plate the plurality of electronic component bodies in which the respective positions of the end surfaces are aligned.

A semiconductor assembly includes a semiconductor package that includes first and second transistor dies embedded within a package body, the first and second transistor dies being arranged laterally side by side within the package body such that a first load terminal of the first transistor die faces an upper surface of the package body and such that a second load terminal of the second transistor die faces the upper surface of the package body, and a discrete capacitor mounted on the semiconductor package such that a first terminal of the discrete capacitor is directly over and electrically connected to the first load terminal of the first semiconductor die and such that a second terminal of the discrete capacitor is directly over and electrically connected with the second load terminal of the second semiconductor die.

The present invention is directed to a multilayer capacitor and a circuit board containing the multilayer capacitor. The capacitor includes a main body containing a set of alternating dielectric layers and internal electrode layers wherein the set contains a first internal electrode layer and a second internal electrode layer and each internal electrode layer includes a top edge, a bottom edge opposite the top edge, and two side edges extending between the top edge and the bottom edge that define a main body of the internal electrode layer. Each internal electrode layer contains at least one lead tab extending from the top edge of the main body of the internal electrode layer and at least one lead tab extending from the bottom edge of the main body of the internal electrode layer, wherein at least one lead tab extending from the top edge of the main body of the internal electrode layer and at least one lead tab extending from the bottom edge of the main body of the internal electrode layer include a lateral edge aligned with a side edge of the main body of the internal electrode layer. External terminals are electrically connected to the internal electrode layers wherein the external terminals are formed on a top surface of the capacitor, a bottom surface of the capacitor opposing the top surface of the capacitor, and extending along an end surface between the top surface and the bottom surface.

The present invention is directed to a multilayer capacitor and a circuit board containing the multilayer capacitor. The capacitor includes a main body containing a set of alternating dielectric layers and internal electrode layers wherein the set contains a first internal electrode layer and a second internal electrode layer and each internal electrode layer includes a top edge, a bottom edge opposite the top edge, and two side edges extending between the top edge and the bottom edge that define a main body of the internal electrode layer. Each internal electrode layer contains at least one lead tab extending from the top edge of the main body of the internal electrode layer and at least one lead tab extending from the bottom edge of the main body of the internal electrode layer, wherein at least one lead tab extending from the top edge of the main body of the internal electrode layer and at least one lead tab extending from the bottom edge of the main body of the internal electrode layer include a lateral edge aligned with a side edge of the main body of the internal electrode layer. External terminals are electrically connected to the internal electrode layers wherein the external terminals are formed on a top surface of the capacitor, a bottom surface of the capacitor opposing the top surface of the capacitor, and extending along an end surface between the top surface and the bottom surface.