In a thin-film capacitor, an electrode terminal layer and an electrode layer of a capacitor portion are connected to electrode terminals by via conductors that is formed to penetrate an insulating layer in a thickness direction thereof, and a short circuit wiring in the thickness direction is realized by the via conductors. In the thin-film capacitor, an increase in the number of terminals in the plurality of electrode terminals is achieved, a decrease in length of a circuit wiring is achieved, and thus a thin-film capacitor with low-ESL has been achieved.

Examples herein include thermally conductive pathways for glass substrates such as used by passive on glass devices that may be used to enhance the thermal conductivity of an integrated POG device. By using a thermally conductive material for passivation of the device pathways during manufacturing, the device pathways may be able to conduct heat away from the device. For example, by using a selected poly (p-phenylene benzobisoxazole) (PBO) based material (e.g., poly-p-phenylene-2, 6-benzobisoxazole) instead of conventional polyimide (PI) materials during a Cu pattern passivation process, the overall thermal performance of the device, may be enhanced.

Examples herein include thermally conductive pathways for glass substrates such as used by passive on glass devices that may be used to enhance the thermal conductivity of an integrated POG device. By using a thermally conductive material for passivation of the device pathways during manufacturing, the device pathways may be able to conduct heat away from the device. For example, by using a selected poly (p-phenylene benzobisoxazole) (PBO) based material (e.g., poly-p-phenylene-2, 6-benzobisoxazole) instead of conventional polyimide (PI) materials during a Cu pattern passivation process, the overall thermal performance of the device, may be enhanced.

A ceramic electronic component includes a ceramic body and first and second outer electrodes. The first and second outer electrodes respectively include first and second resin-containing electrode layers and first and second Ni plating layers. The first and second Ni plating layers are respectively provided on the first and second resin-containing electrode layers. When a thickness of the first or second Ni plating layer is t1 and a distance by which a portion of the first or second Ni plating layer that is in contact with the second principal surface extends in the length direction is t2, t2/t1 is less than about 1.

A ceramic electronic component includes a ceramic body and first and second outer electrodes. The first and second outer electrodes respectively include first and second resin-containing electrode layers and first and second Ni plating layers. The first and second Ni plating layers are respectively provided on the first and second resin-containing electrode layers. When a thickness of the first or second Ni plating layer is t1 and a distance by which a portion of the first or second Ni plating layer that is in contact with the second principal surface extends in the length direction is t2, t2/t1 is less than about 1.

According to one embodiment, a capacitor includes a conductive substrate, a conductive layer, a dielectric layer, and first and second external electrodes. The conductive substrate has a first main surface provided with recess(s), a second main surface, and an end face extending between edges of the first and second main surfaces. The conductive layer covers the first main surface and side walls and bottom surfaces of the recess(s). The dielectric layer is interposed between the conductive substrate and the conductive layer. The first external electrode includes a first electrode portion facing the end face and is electrically connected to the conductive layer. The second external electrode includes a second electrode portion facing the end face and is electrically connected to the conductive substrate.

A high power radiofrequency (RF) capacitor, integrated circuit board/capacitor and methods for manufacture therefor can include a dielectric substrate, and a first metallic layer and a second metallic layer that can be deposited on opposite sides of the dielectric substrate, and a ground plane that can be co-planar with one of the metallic layers. This can establish a broadside coupling capacitance effect between the first metallic layer and the second metallic layer. The first metallic layer and the second metallic layer can have a circular profile when viewed in plan view; alternatively, the first metallic layer and second metallic layer can have a T-shaped profile when viewed in plan view. The desired profile and the desired profile geometry can depend on the design power and operating frequency for the capacitor can depend on whether the capacitor must operate as a series capacitor or a shunt capacitor.

An electronic component includes a multilayer capacitor and an interposer. First and second internal electrodes of the multilayer capacitor are such that 0.95≤{(Wm1+Wm2)/Wa}/{(Lm1+Lm2)/La}≤4.93, in which Lm2 is a distance between a first internal electrode and a fourth surface of a capacitor body, Lm1 is a distance between a second internal electrode and a third surface of the capacitor body opposite the fourth surface in a first direction, Wm1 is a distance between the first or second internal electrode and a second surface of the capacitor body, Wm2 is a distance between the first or second internal electrode and a first surface of the capacitor body opposite the second surface in a third direction, La is a length in the first direction of a region of overlap of the first and second internal electrodes, and Wa is a length in the third direction of the region of overlap.

A chip electronic component includes spacers that each have a predetermined thickness direction dimension on a mounting surface in a direction perpendicular to the mounting surface. The spacers each contain, as a main component, an intermetallic compound containing at least one high-melting-point metal selected from Cu and Ni, and Sn defining a low-melting-point metal.

A vibration device includes a semiconductor substrate having a first surface and a second surface in an obverse-reverse relationship, a vibration element disposed on the first surface, a lid bonded to the first surface, an integrated circuit disposed on the first surface, a terminal disposed on the second surface, a through electrode which penetrates the semiconductor substrate, and is configured to electrically couple the terminal and the integrated circuit to each other, and a first capacitor which is provided with a first recess provided to the semiconductor substrate and opening in the first surface, an insulating film disposed on an inside surface of the first recess, and an electrically-conductive material filling the first recess, and has a first capacitance between the electrically-conductive material and the semiconductor substrate, wherein the electrically-conductive material does not have contact with the terminal at the second surface side.