MIM capacitors using low temperature sub-nanometer periodic stack dielectrics (SN-PSD) containing repeating units of alternating high dielectric constant materials sublayer and low leakage dielectric sublayer are provided. Every sublayer has thickness less than 1 nm (sub nanometer). The high dielectric constant materials could be one or more different materials. The low leakage dielectric materials could be one or more different materials. For the SN-PSD containing more than two different materials, those materials are deposited in sequence with the leakage current of the materials from the lowest to the highest and then back to the second-lowest, or with the energy band gap of the materials from the widest to the narrowest and then back to the second widest in each periodic cell. A layer of low leakage current dielectric materials is deposited on and/or under SN-PSD. The dielectric constant of SN-PSD is much larger than that of the component oxides and can be readily deposited at 250 C. using atomic layer deposition (ALD). The ALD deposition cycle could be 20-1000 cycles. The deposition technology is not limited to ALD, could be thermal oxidation, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD) and other thermal source assisted deposition.

A chip electronic component includes spacers that each have a predetermined thickness direction dimension on a mounting surface in a direction perpendicular to the mounting surface. The spacers each contain, as a main component, an intermetallic compound containing at least one high-melting-point metal selected from Cu and Ni, and Sn defining a low-melting-point metal.

A multilayer ceramic electronic component includes a multilayer body including two major surfaces opposite to each other in a layer stacking direction, two side surfaces opposite to each other in a widthwise direction orthogonal or substantially orthogonal to the layer stacking direction, and two end surfaces opposite to each other in a lengthwise direction orthogonal or substantially orthogonal to the layer stacking direction and the widthwise direction, and external electrodes provided on the two end surfaces. A method for manufacturing the multilayer ceramic capacitor component includes preparing a plurality of multilayer bodies, stacking the plurality of multilayer bodies via a binder, rotating the plurality of multilayer bodies by about 90 with the lengthwise direction defining and functioning as an axis of rotation, and providing a side gap portion; and removing the binder from the multilayer body provided with the side gap portion.

A chip component includes a substrate that has a first surface and a second surface on a side opposite to the first surface, a plurality of wall portions that are formed on a side of the first surface by using a part of the substrate, that have one end portion and one other end portion, and that are formed of a plurality of pillar units, a support portion that is formed around the wall portions by using a part of the substrate and that is connected to at least one of the end portion and the other end portion of the wall portions, and a capacitor portion formed by following a surface of the wall portion, in which each of the pillar units includes a central portion and three convex portions that extend from the central portion in three mutually different directions in a plan view and in which the wall portion is formed by a connection between the convex portions of the pillar units that adjoin each other.

A chip component includes a substrate that has a first surface and a second surface on a side opposite to the first surface, a plurality of wall portions that are formed on a side of the first surface by using a part of the substrate, that have one end portion and one other end portion, and that are formed of a plurality of pillar units, a support portion that is formed around the wall portions by using a part of the substrate and that is connected to at least one of the end portion and the other end portion of the wall portions, and a capacitor portion formed by following a surface of the wall portion, in which each of the pillar units includes a central portion and three convex portions that extend from the central portion in three mutually different directions in a plan view and in which the wall portion is formed by a connection between the convex portions of the pillar units that adjoin each other.

According to one embodiment, a capacitor includes a conductive substrate, a conductive layer, a dielectric layer, and first and second external electrodes. The conductive substrate has a first main surface provided with recess(s), a second main surface, and an end face extending between edges of the first and second main surfaces. The conductive layer covers the first main surface and side walls and bottom surfaces of the recess(s). The dielectric layer is interposed between the conductive substrate and the conductive layer. The first external electrode includes a first electrode portion facing the end face and is electrically connected to the conductive layer. The second external electrode includes a second electrode portion facing the end face and is electrically connected to the conductive substrate.

A multilayer electronic component includes a body, a protrusion disposed on at least one surface of the body, and an external electrode having an electrode layer disposed on a side surface of the body and extending to be in contact with a side surface of the protrusion and a conductive resin layer disposed on the electrode layer and extending to cover a portion of the protrusion.

A capacitor component includes: a semiconductor substrate including first and second portions, a trench penetrating through the substrate from one surface of the substrate to the other surface of the substrate to separate the first and second portions of the substrate from each other, a dielectric layer disposed in the trench and on the one surface of the substrate; a first pad electrode and a second pad electrode spaced apart from each other, and penetrating through the dielectric layer to be in contact with the first and second portions of the substrate, respectively, and a passivation layer disposed on the dielectric layer, covering portions of the first pad electrode and the second pad electrode, and exposing at least a portion of each of the first pad electrode and the second pad electrode.

A capacitor component includes: a semiconductor substrate including first and second portions, a trench penetrating through the substrate from one surface of the substrate to the other surface of the substrate to separate the first and second portions of the substrate from each other, a dielectric layer disposed in the trench and on the one surface of the substrate; a first pad electrode and a second pad electrode spaced apart from each other, and penetrating through the dielectric layer to be in contact with the first and second portions of the substrate, respectively, and a passivation layer disposed on the dielectric layer, covering portions of the first pad electrode and the second pad electrode, and exposing at least a portion of each of the first pad electrode and the second pad electrode.

A multilayer ceramic capacitor has a body including first and second internal electrodes laminated with a dielectric layer interposed therebetween, and having fifth and sixth surfaces opposing each other, third and fourth surfaces opposing each other, and first and second surfaces opposing each other. A first through-electrode penetrates through the body to be connected to the first internal electrode, and a second through-electrode penetrates through the body to be connected to the second internal electrode. First and second external electrodes are disposed on the first and second surfaces, respectively, and third and fourth external electrodes are disposed on the first and second surfaces, respectively, to be spaced apart from the first and second external electrodes. Each of the first to fourth external electrodes is a respective sintered electrode including nickel.