The present invention provides a non-volatile memory and a manufacturing method for the same. In the non-volatile memory, a floating gate structure has a first sharp portion and a second sharp portion, and a corner formed by a side surface of the floating gate structure and a part of a top surface of the floating gate structure is not covered by a control gate structure. The corner is connected between the first sharp portion and one end of the second sharp portion. A tunneling dielectric layer of an erasing gate structure covers the first sharp portion, the second sharp portion, and a tip part of the corner.

An atomic layer deposition apparatus includes a chamber including a plurality of regions; and a heating device respectively providing specific temperature ranges for the plurality of regions. By flowing precursor gases at different flow rates in the different regions, thin films can be simultaneously formed in the different regions having different film thicknesses.

The present invention provides a non-volatile memory and a manufacturing method for the same. In the non-volatile memory, a floating gate structure has a first sharp portion and a second sharp portion, and a corner formed by a side surface of the floating gate structure and a part of a top surface of the floating gate structure is not covered by a control gate structure. The corner is connected between the first sharp portion and one end of the second sharp portion. A tunneling dielectric layer of an erasing gate structure covers the first sharp portion, the second sharp portion, and a tip part of the corner.

Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a semiconductive substrate. A donor-supply layer is over the semiconductive substrate. The donor-supply layer includes a top surface. A gate structure, a drain, and a source are over the donor-supply layer. A passivation layer covers conformally over the gate structure and the donor-supply layer. A gate electrode is over the gate structure. A field plate is disposed on the passivation layer between the gate electrode and the drain. The field plate includes a bottom edge. The gate electrode having a first edge in proximity to the field plate, the field plate comprising a second edge facing the first edge, a horizontal distance between the first edge and the second edge is in a range of from about 0.05 to about 0.5 micrometers.

For enhancing productivity, an apparatus comprises a vertical type process furnace configured to simultaneously process N substrates (1<N); a loading chamber provided under the vertical type process furnace and configured to transfer the substrate retainer into or out of the vertical type process furnace; a plurality of single-wafer type process furnaces provided adjacent to the loading chamber, each of the plurality of single-wafer type process furnaces being stacked in at least 2 stages and configured to simultaneously process M substrates (M<N); and a transfer chamber module provided adjacent to the loading chamber and the plurality of the single-wafer type process furnaces and provided with a transfer device.

A micro-LED display device includes a substrate; a first insulating layer on the substrate and including a first region and a second region; and a micro-LED in the first region, wherein the first region has a first hydrophilicity, and the second region has a second hydrophilicity that is less than the first hydrophilicity.

A structural body includes a first dielectric layer and a second dielectric layer which is in contact with the first dielectric layer and which has a refractive index different from that of the first dielectric layer. The second dielectric layer includes at least two dielectric films different in hydrogen concentration from each other. The interface between the first dielectric layer and the second dielectric layer has periodic first irregularities.

A semiconductor device includes a substrate, a peripheral structure, a lower insulating layer, and a stack. The substrate includes a peripheral circuit region and a cell array region. The peripheral structure is on the peripheral circuit region. The lower insulating layer covers the peripheral circuit region and the cell array region and has a protruding portion protruding from a flat portion. The stack is on the lower insulating layer and the cell array region, and includes upper conductive patterns and insulating patterns which are alternately and repeatedly stacked.

A silicon layer etchant composition and associated methods, the composition including about 1 wt % to about 20 wt % of an alkylammonium hydroxide; about 1 wt % to about 30 wt % of an amine compound; about 0.01 wt % to about 0.2 wt % of a nonionic surfactant including both a hydrophobic group and a hydrophilic group; and water, all wt % being based on a total weight of the silicon layer etchant composition.

A substrate processing method includes: maintaining an atmosphere in contact with at least a surface of a substrate on which a first material that is a metal and a second material that is a material other than the first material are exposed, as a deoxidized atmosphere; supplying a film forming material, which selectively forms a film on the first material among the first material and the second material, to the surface of the substrate in a state where the deoxidized atmosphere is maintained by the maintaining; performing a surface treatment of the second material in a state where the film is formed on a surface of the first material supplied in the supplying the film forming material; and removing the film from the surface of the first material after the performing the surface treatment.