A method for making a heteroepitaxial layer. The method comprises providing a semiconductor substrate. A seed area delineated with a selective growth mask is formed on the semiconductor substrate. The seed area comprises a first material and has a linear surface dimension of less than 100 nm. A heteroepitaxial layer is grown on the seed area, the heteroepitaxial layer comprising a second material that is different from the first material. Devices made by the method are also disclosed.

The present invention provides a non-volatile memory and a manufacturing method for the same. In the non-volatile memory, a floating gate structure has a first sharp portion and a second sharp portion, and a corner formed by a side surface of the floating gate structure and a part of a top surface of the floating gate structure is not covered by a control gate structure. The corner is connected between the first sharp portion and one end of the second sharp portion. A tunneling dielectric layer of an erasing gate structure covers the first sharp portion, the second sharp portion, and a tip part of the corner.

A sensing amplification circuit includes a sensing amplifier and a trigger control circuit. The sensing amplifier receives a data voltage and a reference voltage, and outputs a first data signal and a second data signal by comparing the data voltage and the reference voltage. The trigger control circuit includes a logic circuit and a set-reset latch. The logic circuit receives the first data signal and the second data signal, and changes a first control signal from a first voltage level to a second voltage level when one of the first data signal and the second data signal changes its state. The first set-reset latch receives the first control signal and a second control signal, and generates a trigger signal to enable the sensing amplifier when the second control signal changes state and disable the sensing amplifier when the first control signal changes state.

A gas shower head includes a plate, a plurality of central holes disposed in a central region of the plate, and a plurality of peripheral holes disposed in a peripheral region of the plate. The central holes are configured to form a first portion of a material film, and the peripheral holes are configured to form a second portion of the material film. A hole density in the peripheral region is greater than a hole density in the central region. The first portion of the material film includes a first thickness corresponding to the hole density in central region, and the second portion of the material film includes a second thickness corresponding to the hole density in peripheral region and greater than the first thickness.

The present invention provides a raw material for thin film formation containing a compound represented by the following General Formula (1), a method for manufacturing a thin film using the raw material, and a novel compound represented by General Formula (2) in this specification:

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wherein, X represents a halogen atom, and R represents a primary alkyl group or secondary butyl group having 1 to 5 carbon atoms.

A method for fabricating a semiconductor device includes forming a via in a first dielectric layer arranged on a metal layer. The via exposes a portion of the metal layer. The method includes forming a trench in the first dielectric layer. The method further includes depositing, by a selective process, a second dielectric layer on the first dielectric layer such that the second dielectric layer lines sidewalls of the via and the trench and is selectively deposited onto the first dielectric layer.

A method for manufacturing a semiconductor device includes forming a semiconductor layer including an oxide semiconductor as a main component and forming an insulator layer on a surface of the semiconductor layer. The insulator layer includes silicon oside as a main component and has a hydrogen atom concentration that is less than or equal to 110.sup.21 atoms/cm.sup.3.

The present invention provide an IC die, including an underlay; an active component; an interconnection layer, covering the active component, where the interconnection layer includes multiple metal layers and multiple dielectric layers, the multiple metal layers and the multiple dielectric layers are alternately arranged, a metal layer whose distance to the active component is the farthest in the multiple metal layers includes metal cabling and a metal welding pad; and a heat dissipation layer, where the heat dissipation layer covers a region above the interconnection layer except a position corresponding to the metal welding pad, the heat dissipation layer is located under a package layer, the package layer includes a plastic packaging material, and the heat dissipation layer includes an electrical-insulating material whose heat conductivity is greater than a preset value.

The disclosed technology relates generally to semiconductor devices, and more particularly to field-effect transistors (FETs) comprising nanostructures, such as nanowires, fins, and two dimensional materials. In an aspect, a FET device comprises a substrate having an insulating surface and a vertical structure extending in a direction substantially perpendicular to the insulating surface, where the vertical structure has at least outer surfaces formed of an insulating material. The FET device additionally includes a thin layer of two-dimensional (2D) material enveloping the vertical structure and at least part of the insulating surface. The FET device additionally includes two electrodes in electrical contact with the thin layer of 2D material, where one of the electrodes is formed on top of the vertical structure. The FET device additionally includes a control electrode configured to apply an electric field across the thin layer of 2D material to cause a change in the conductivity of the thin layer of 2D material. The FET device further includes at least one stack of materials configured to provide different regions of band bending in the thin layer of 2D material by capacitive coupling.

A multi-scale manufacturing system comprising a centrally located multi-axis and multi-dimensional first manipulating component associated with a housing for manipulating a substrate and a template, a control subsystem coupled to the first manipulating component for controlling movement thereof, a pre-alignment subsystem for pre-aligning the substrate and the template, an assembly station for applying nanomaterial to the template, an alignment station for aligning the template and the substrate together to form a workpiece assembly, and a transfer subsystem for applying pressure to the workpiece assembly for transferring the nanomaterial from the template to the substrate.