A method for making a heteroepitaxial layer. The method comprises providing a semiconductor substrate. A seed area delineated with a selective growth mask is formed on the semiconductor substrate. The seed area comprises a first material and has a linear surface dimension of less than 100 nm. A heteroepitaxial layer is grown on the seed area, the heteroepitaxial layer comprising a second material that is different from the first material. Devices made by the method are also disclosed.

A method for making a heteroepitaxial layer. The method comprises providing a semiconductor substrate. A seed area delineated with a selective growth mask is formed on the semiconductor substrate. The seed area comprises a first material and has a linear surface dimension of less than 100 nm. A heteroepitaxial layer is grown on the seed area, the heteroepitaxial layer comprising a second material that is different from the first material. Devices made by the method are also disclosed.

A method for making a heteroepitaxial layer. The method comprises providing a semiconductor substrate. A seed area delineated with a selective growth mask is formed on the semiconductor substrate. The seed area comprises a first material and has a linear surface dimension of less than 100 nm. A heteroepitaxial layer is grown on the seed area, the heteroepitaxial layer comprising a second material that is different from the first material. Devices made by the method are also disclosed.

A method for making a heteroepitaxial layer. The method comprises providing a semiconductor substrate. A seed area delineated with a selective growth mask is formed on the semiconductor substrate. The seed area comprises a first material and has a linear surface dimension of less than 100 nm. A heteroepitaxial layer is grown on the seed area, the heteroepitaxial layer comprising a second material that is different from the first material. Devices made by the method are also disclosed.

A silicon carbide semiconductor device includes a semiconductor element with a MOS structure having: a substrate; a drift layer on the substrate; a base region on the drift layer; a source region on the base region; a trench gate structure having a gate insulation film and a gate electrode in a gate trench disposed from a surface of the source region to be deeper than the base region; an interlayer insulation film covering the gate electrode and the gate insulation film; a source electrode on the interlayer insulation film, the source region and the base region; and a drain electrode. The semiconductor element flows a current when a gate voltage is applied to the gate electrode and a channel region is provided in a portion of the base region in contact with the trench gate structure.

A memory circuit includes a memory cell, a first program driver, a second program driver, and a sensing amplifier. A method for operating the memory circuit includes, during a program operation of the memory cell, providing a program voltage to the memory cell, enabling the first program driver to drive the first local bit line to be at a low voltage, enabling the second program driver, disabling the first program driver, and enabling the sensing amplifier to verify whether the first memory cell has been programmed or not. The second program driver has a weaker driving ability than the first program driver.

A memory device and a manufacturing method thereof are provided. The memory device includes a first gate structure, a second gate structure, an oxide layer and a nitride layer. The first gate structure and the second gate structure are disposed on a substrate. The oxide layer covers the first gate structure. The nitride layer is disposed on the substrate and covers the oxide and the second gate structure. The refraction index of a portion of the nitride layer adjacent to an interface between the nitride layer and each of the first gate structure and the second gate structure is about 5% to 10% less than the refraction index of the remaining portion of the nitride layer.

A method for fabricating a semiconductor device includes forming a via in a first dielectric layer arranged on a metal layer. The via exposes a portion of the metal layer. The method includes forming a trench in the first dielectric layer. The method further includes depositing, by a selective process, a second dielectric layer on the first dielectric layer such that the second dielectric layer lines sidewalls of the via and the trench and is selectively deposited onto the first dielectric layer.

Described herein is a technique capable of suppressing variations or deterioration in a processing rate between a plurality of substrates due to temperature. According to one aspect of the technique of the present disclosure, there is provided a substrate processing apparatus including: a process vessel constituting at least a part of a process chamber where a substrate is processed; a plasma generator comprising a coil provided to be wound around an outer periphery of the process vessel and a high frequency power supply configured to supply high frequency power to the coil; a substrate support provided in the process chamber and below a lower end of the coil; a heater provided in the substrate support; and a temperature sensor configured to measure a temperature of a portion of the process vessel located above an upper end of the coil.

A method for making a heteroepitaxial layer. The method comprises providing a semiconductor substrate. A seed area delineated with a selective growth mask is formed on the semiconductor substrate. The seed area comprises a first material and has a linear surface dimension of less than 100 nm. A heteroepitaxial layer is grown on the seed area, the heteroepitaxial layer comprising a second material that is different from the first material. Devices made by the method are also disclosed.