An element-accommodating package which can improve frequency characteristics of an element-accommodating package having a coaxial connector, and a mounting structure are provided. An element-accommodating package includes a metallic substrate, a frame, a first coaxial connector, a second coaxial connector, and a circuit board. A groove is provided between one side of the frame and a side surface of the circuit board and between a first signal line and a second signal line.

A semiconductor module includes a rectangular base plate; a substrate which is placed on the base plate and on which a circuit including a semiconductor chip and so forth is formed; a rectangular parallelepiped case made of resin that is attached to the base plate and houses the substrate within; and a plurality of external terminals lower ends of which are fixed to the substrate with upper ends thereof being exposed on a top face of the case. The case is provided with a first case opening portion and a second case opening portion that are respectively formed by cutting off a front face and a rear face of the case from an upper edge thereof along a longitudinal direction thereof; and the top face of the case between the first case opening portion and the second case opening portion includes an external terminal holding portion to hold the plurality of external terminals along the longitudinal direction with the upper ends thereof being exposed. A sealing material is injected from the first case opening portion and the second case opening portion onto a top face of the substrate, and thereby the semiconductor module is sealed.

A lens cap for a transistor outline (TO) package is provided that has an inner diameter of less than 4 mm. The lens cap includes a metal shell with a wall thickness of less than 0.2 mm and a thinned area surrounding the lens so that in the thinned area the wall thickness is reduced by at least 35%.

A device is provided. The device may include one or more of a package base, a substrate, a die secured to the substrate, a plurality of bond connections, and a package lid. The package base includes a plurality of package leads and a package base body. The package base body includes an open cavity disposed through the entire package base body, a plurality of package bond pads, disposed within a periphery of the open cavity, and a mounting shelf, disposed within the open cavity. The substrate is secured to the mounting shelf, and includes a plurality of substrate bond pads. The plurality of bond connections are configured to provide electrical connections between one or more of the die, the substrate bond pads, and the package bond pads. The package lid is secured over the open cavity to the package base body.

An electronic device includes a circuit board with an insulating substrate, a wiring at the substrate, an electronic component mounted at the substrate and electrically connected to the wiring, at least one through hole through the substrate from one surface to an opposite surface of the one surface of the substrate, and a conductive member arranged at a surface of the through hole and electrically connected to the wiring; and further includes: a sealing resin; and a cap including an annular connection with a part connected to the substrate and a recess recessed from the annular connection. Furthermore, in the cap, at least a part of the connection is connected to the substrate, the cap being sealed integrally with the electronic component by the sealing resin while arranging a space communicating with the through hole; and a terminal is inserted into the through hole and electrically connected to the wiring.

On a typical motherboard the processor and memory are separated by a printed circuit data bus that traverses the motherboard. Throughput, or data transfer rate, on the data bus is much lower than the rate at which a modern processor can operate. The difference between the data bus throughput and the processor speed significantly limits the effective processing speed of the computer when the processor is required to process large amounts of data stored in the memory. The processor is forced to wait for data to be transferred to or from the memory, leaving the processor under-utilized. The delays are compounded in a distributed computing system including a number of computers operating in parallel. The present disclosure describes systems, method and apparatus that tend to alleviate delays so that memory access bottlenecks are not compounded within distributed computing systems.

A device (2) is formed on a main surface of a substrate (1). The main surface of the substrate (1) is bonded to the undersurface of the counter substrate (14) via the bonding member (11,12,13) in a hollow state. A circuit (17) and a bump structure (26) are formed on the top surface of the counter substrate (14). The bump structure (26) is positioned in a region corresponding to at least the bonding member (11,12,13), and has a higher height than that of the circuit (17).

The present disclosure provides a semiconductor package structure and a method of manufacturing the same. The semiconductor package structure includes a substrate, a first electronic component, an interlayer, a third electronic component and an encapsulant. The first electronic component is disposed on the substrate. The first electronic component has an upper surface and a lateral surface and a first edge between the upper surface and the lateral surface. The interlayer is on the upper surface of the first electronic component. The third electronic component is attached to the upper surface of the first electronic component via the interlayer. The encapsulant encapsulates the first electronic component and the interlayer. The interlayer does not contact the lateral surface of the first electronic component.

An integrated device package is disclosed. The integrated device package can include a packaging structure defining a cavity. An integrated device die can be disposed at least partially within the cavity. A gel can be disposed within the cavity surrounding the integrated device. A portion of the gel can be disposed between a lower surface of the integrated device die and an upper surface of the packaging structure within the cavity.

A solid-state storage device includes a housing, a wiring board and a semiconductor package unit. The housing is formed with a heat-dissipating recess thereon. The wiring board is fixed in the housing. One side of the semiconductor package unit is mounted on the wiring board, and the other side of the semiconductor package unit is embedded in the heat-dissipating recess. A top surface and lateral surfaces surrounding the top surface of the semiconductor package unit are all thermally connected to the housing in the heat-dissipating recess.