A method of manufacturing a semiconductor device is described. A semiconductor substrate is provided. The semiconductor substrate includes a semiconductor substrate layer and a semiconductor device layer. The method includes transforming areas of the semiconductor device layer into dicing areas which can be removed by etching, and removing the semiconductor substrate layer and the dicing areas by using etching.

An electronic module for a half-bridge circuit includes a base substrate with an insulating layer between a first metal layer and a second metal layer. A trench formed through the first metal layer electrically isolates first, second, and third portions of the first metal layer from one another. A high-side switch includes an enhancement-mode transistor and a depletion-mode transistor. The depletion-mode transistor includes a III-N material structure on an electrically conductive substrate. A drain electrode of the depletion-mode transistor is connected to the first portion, a source electrode of the enhancement-mode transistor is connected to the second portion, a drain electrode of the enhancement-mode transistor is connected to a source electrode of the depletion-mode transistor, a gate electrode of the depletion-mode transistor is connected to the electrically conductive substrate, and the electrically conductive substrate is connected to the second portion.

Two conductive reference layers are embedded in a semiconductor package substrate. The embedded reference layers facilitate low electromagnetic noise coupling between adjacent signals for semiconductor device package.

A circuit base of the present disclosure includes a base made of ceramic, a joint layer located on the base, and a metal layer located on the joint layer. The metal layer contains copper. The joint layer contains aluminum, silicon, and oxygen.

The present invention provides a power semiconductor module, including a substrate having an electric insulating main layer being provided with a structured top metallization and with a bottom metallization, wherein the top metallization is provided with at least one power semiconductor device and at least one contact area, wherein the main layer together with its top metallization and the at least one power semiconductor device is embedded in a mold compound such that the mold compound includes at least one opening for contacting the at least one contact area, and wherein power semiconductor module includes a housing with circumferential side walls, wherein the side walls are positioned above the main layer of the substrate so that the side walls are only present in a space above a plane through the main layer of the substrate.

In some examples, a sensor package includes a semiconductor die having a sensor; a mold compound covering a portion of the semiconductor die; and a cavity formed in a top surface of the mold compound, the sensor being in the cavity. The sensor package includes an adhesive abutting the top surface of the mold compound, and a semi-permeable film abutting the adhesive and covering the cavity. The semi-permeable film is approximately flush with at least four edges of the top surface of the mold compound.

A structure includes: a plurality of through holes that are provided to an insulating base and penetrate the insulating base in the thickness direction; conductive paths that are constituted of a conductive substance filling the plurality of through-holes; and insulators with which the plurality of through-holes are filled and are constituted of an insulating substance different from that of the insulating base. Both ends of the respective conductive paths are provided with protrusions that protrude from each surface of the insulating base in the thickness direction. Both ends of the insulators are flush with each surface of the insulating base in the thickness direction, protrude with respect to the surface in the thickness direction, or are recessed from the surface in the thickness direction.

What is provided is a method of manufacturing an insulating circuit board with a heatsink including an insulating circuit board and a heatsink, the heatsink being bonded to the metal layer side of the insulating circuit board, the metal layer being formed of aluminum, and a bonding surface of the heatsink with the insulating circuit board being formed of an aluminum alloy having a solidus temperature of 650° C. or lower. This method includes a high alloy element concentration portion forming step (S02) of forming a high alloy element concentration portion and a heatsink bonding step (S03) of bonding the heatsink, in which a ratio tb/ta of a thickness tb of the brazing material layer to a thickness to of the core material in the clad material is in a range of 0.1 to 0.3.

A carrier board and a power module using the same are disclosed. The carrier board includes a main body, two metal-wiring layers and at least one metal block. The main body includes at least two terminals and a surface. The two terminals are disposed on the surface. The two metal-wiring layers are disposed on the main body to form two parts of metal traces connected to the two terminals, respectively. The at least one metal block is embedded in the main body and connected to one of the two terminals. A thickness of the two parts of metal traces is less than that of the metal block. The two terminals connected by the two parts of metal traces have a loop inductance less than or equal to 1.4 nH calculated at a frequency greater than 1 MHz.

Provided a package substrate including an insulation substrate, a conductive layer provided in the insulation substrate, upper pads provided on an upper surface of the insulation substrate and electrically connected to the conductive layer, lower pads provided on a lower surface of the insulation substrate and electrically connected to the conductive layer, and at least one trench provided at a portion of the insulation substrate adjacent to at least one of the upper pads and configured to block stress, which is generated by an expansion of the insulation substrate, from spreading to the at least one of the upper pads.