H01L23/373

THERMALLY ENHANCED PACKAGE TO REDUCE THERMAL INTERACTION BETWEEN DIES

A method of reducing heat flow between IC chips and the resulting device are provided. Embodiments include attaching plural IC chips to an upper surface of a substrate; forming a lid over the IC chips; and forming a slit through the lid at a boundary between adjacent IC chips.

HEAT SPREADERS WITH INTEGRATED PREFORMS

Embodiments of heat spreaders with integrated preforms, and related devices and methods, are disclosed herein. In some embodiments, a heat spreader may include: a frame formed of a metal material, wherein the metal material is a zinc alloy or an aluminum alloy; a preform secured in the frame, wherein the preform has a thermal conductivity higher than a thermal conductivity of the metal material; and a recess having at least one sidewall formed by the frame. The metal material may have an equiaxed grain structure. In some embodiments, the equiaxed grain structure may be formed by squeeze-casting or rheocasting the metal material.

Methods for multi-wafer stacking and dicing
11710717 · 2023-07-25 · ·

A method includes providing a structure including a carrier wafer, and a first device wafer with an adhesion layer between the carrier wafer and the first device wafer; and forming a plurality of first ablation structures in the structure, each of the plurality of first ablation structures extending through the first device wafer, the adhesion layer and a portion of the carrier wafer. Each of the plurality of first ablation structures has a portion inside the carrier wafer with a depth no greater than one half of a thickness of the carrier wafer. The first device wafer includes a plurality of first dies, each pair of adjacent first dies being separated by one of the plurality of first ablation structures. The plurality of first ablation structures are formed by either laser grooving or mechanical sawing.

Microelectronic package with underfilled sealant

Embodiments may relate to a method of forming a microelectronic package with an integrated heat spreader (IHS). The method may include placing a solder thermal interface material (STIM) layer on a face of a die that is coupled with a package substrate; coupling the IHS with the STIM layer and the package substrate such that the STIM is between the IHS and the die; performing formic acid fluxing of the IHS, STIM layer, and die; and dispensing, subsequent to the formic acid fluxing, sealant on the package substrate around a periphery of the IHS.

Semiconductor module

A semiconductor module includes a semiconductor element, a substrate on which the semiconductor module is mounted, a heat radiating plate on which the substrate is mounted, a resin case, and a first main current electrode and a second main current electrode, in which in the first main current electrode and the second main current electrode, one end of each thereof is joined to a circuit pattern on the substrate, an other end of each thereof is extended through and incorporated in a side wall of the resin case so as to project outward of the resin case, and each thereof has at least a portion of overlap at which a part thereof overlaps in parallel with each other with a gap therebetween, and each thereof has a slope portion provided between an external projection portion and an internal projection portion.

BUILD-UP PACKAGE FOR INTEGRATED CIRCUIT DEVICES, AND METHODS OF MAKING SAME
20230005802 · 2023-01-05 ·

A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a perimeter of the die, the molded body having lips that are positioned above a portion of the active surface of the die. Another illustrative example includes an integrated circuit die having an active surface, a molded body extending around a perimeter of the die and a CTE buffer material formed around at least a portion of the perimeter of the die adjacent the active surface of the die, wherein the CTE buffer material is positioned between a portion of the die and a portion of the molded body and wherein the CTE buffer material has a coefficient of thermal expansion that is intermediate a coefficient of thermal expansion for the die and a coefficient of thermal expansion for the molded body.

BUILD-UP PACKAGE FOR INTEGRATED CIRCUIT DEVICES, AND METHODS OF MAKING SAME
20230005802 · 2023-01-05 ·

A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a perimeter of the die, the molded body having lips that are positioned above a portion of the active surface of the die. Another illustrative example includes an integrated circuit die having an active surface, a molded body extending around a perimeter of the die and a CTE buffer material formed around at least a portion of the perimeter of the die adjacent the active surface of the die, wherein the CTE buffer material is positioned between a portion of the die and a portion of the molded body and wherein the CTE buffer material has a coefficient of thermal expansion that is intermediate a coefficient of thermal expansion for the die and a coefficient of thermal expansion for the molded body.

DUAL-SIDE COOLING SEMICONDUCTOR PACKAGES AND RELATED METHODS

A dual-side cooling (DSC) semiconductor package includes a first metal-insulator-metal (MIM) substrate having a first insulator layer, first metallic layer, and second metallic layer. A second MIM substrate includes a second insulator layer, third metallic layer, and fourth metallic layer. The third metallic layer includes a first portion having a first contact area and a second portion, electrically isolated from the first portion, having a second contact area. A semiconductor die is coupled with the second metallic layer and is directly coupled with the third metallic layer through one or more solders, sintered layers, electrically conductive tapes, solderable top metal (STM) layers, and/or under bump metal (UBM) layers. The first contact area is electrically coupled with a first electrical contact of the die and the second contact area is electrically coupled with a second electrical contact of the die. The first and fourth metallic layers are exposed through an encapsulant.

SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
20230238297 · 2023-07-27 · ·

Provided is a semiconductor package and a method of manufacturing the same, wherein in the semiconductor package, an area on a surface of a heat release metal layer pressed by a molding die is expanded and the molding die directly and uniformly compresses an upper substrate and/or a lower substrate, each of which does not include heat release posts so that contamination of a substrate occurring due to a molding resin may be prevented and molding may be stably performed.

POWER MODULE
20230238361 · 2023-07-27 ·

A power module is provided. The power module includes an electrical interconnection assembly and at least one electronic element group. The electrical interconnection assembly includes a conductive structure and a circuit board. The conductive structure includes a first conductive member and a second conductive manner insulated from each other and arranged side by side. The circuit board is disposed on the conductive structure. The circuit board has an opening. The at least one electronic element group includes a power element that includes a first pad, a second pad, and a third pad. The first and second pads pass through the opening, and are respectively and electrically connected to the first and second conductive members. The third pad is disposed on the circuit board.