A semiconductor device includes a semiconductor chip, a bonding member, and a planar laminated substrate having the semiconductor chip bonded to a front surface thereof via the bonding member. The laminated substrate includes a planar ceramic board, a high-potential metal layer, a low-potential metal layer, an intermediate layer. The planar ceramic board contains a plurality of ceramic particles. The high-potential metal layer contains copper and is bonded to a first main surface of the ceramic board. The low-potential metal layer contains copper, is bonded to a second main surface of the ceramic board, and has a potential lower than a potential of the first main surface of the high-potential metal layer. The intermediate layer is provided between the second main surface and the low-potential metal layer and includes a first oxide that contains at least either magnesium or manganese.

A semiconductor device package comprises a semiconductor switching device having a body, including a first side, and an opposing second side coupled to a substrate. A gate terminal is defined on the semiconductor switching device body first side, the gate terminal having a first side, and an opposing second side facing the semiconductor switching device body. A first gate resistor is disposed on the gate terminal first side, and coupled electrically in series with the gate terminal.

A semiconductor structure including a substrate and a deep trench isolation structure is provided. The deep trench isolation structure is disposed in the substrate and is not electrically connected to any device. The deep trench isolation structure includes a heat dissipation layer and a dielectric liner layer. The heat dissipation layer is disposed in the substrate. The dielectric liner layer is disposed between the heat dissipation layer and the substrate.

Exfoliated graphite materials, and composite materials including exfoliated graphite, having enhanced through-plane thermal conductivity can be used in thermal management applications and devices. Methods for making such materials and devices involve processing exfoliated graphite materials such as flexible graphite to orient or re-orient the graphite flakes in one or more regions of the material.

Exfoliated graphite materials, and composite materials including exfoliated graphite, having enhanced through-plane thermal conductivity can be used in thermal management applications and devices. Methods for making such materials and devices involve processing exfoliated graphite materials such as flexible graphite to orient or re-orient the graphite flakes in one or more regions of the material.

A composite assembly of three stacked joining partners, and a corresponding method. The three stacked joining partners are materially bonded to one another by an upper solder layer and a lower solder layer. An upper joining partner and a lower joining partner are fixed in their height and have a specified distance from one another. The upper solder layer is fashioned from a first solder agent, having a first melt temperature, between the upper joining partner and a middle joining partner. The second solder layer is fashioned from a second solder agent, having a higher, second melt temperature, between the middle joining partner and the lower joining partner. The upper joining partner has an upwardly open solder compensating opening filled with the first solder agent, from which, to fill the gap between the upper joining partner and the middle joining partner, the first solder agent subsequently flows into the gap.

A power semiconductor module may include one or more of the following: a main substrate having at least one metallization layer; a semiconductor switch chip with a positive terminal on a positive terminal side and a negative terminal on a negative terminal side opposite to the positive terminal side adapted for switching a current from the positive terminal to the negative terminal; a diode chip with an anode on an anode side and a cathode on a cathode side opposite to the anode side adapted for blocking a current from the cathode to the anode, where the diode chip is bonded to the second area; a heat sink connected to the main substrate opposite to the semiconductor switch chip and the diode chip; and an auxiliary substrate having at least one metallization layer.

A semiconductor package can include a semiconductor die stack including a top die and one or more core dies below the top die. The semiconductor package can further include a metal heat sink plated on a top surface of the top die and have a plurality of side surfaces coplanar with corresponding ones of a plurality of sidewalls of the semiconductor die stack. A molding can surround the stack of semiconductor dies and the metal heat sink, the molding including a top surface coplanar with an exposed upper surface of the metal heat sink. The top surface of the molding and the exposed upper surface of the metal heat sink are both mechanically altered. For example, the metal heat sink and the molding can be simultaneously ground with a grinding disc and can show grinding marks as a result.

A semiconductor package device includes a substrate, an electronic component, and a thermal conductive layer. The electronic component is disposed on the substrate and includes a first surface facing away from the substrate. The thermal conductive layer is disposed above the first surface of the electronic component. The thermal conductive layer includes a plurality of portions spaced apart from each other.

A ceramic substrate according to the present invention includes: a ceramic base material; an electrode pattern formed on the ceramic base material; and at least one spacer arranged in any one of regions in the ceramic base material and the electrode pattern, in which a semiconductor chip is mounted.