An apparatus for cooling electronic circuitry components and photonic components. In examples of the disclosure at least one photonic component is positioned overlaying at least one electronic circuitry component. In examples of the disclosure there is also provided a spacer for spacing the at least one electronic circuitry component and the at least one photonic component, wherein the spacer for spacing are thermally insulating. In examples of the disclosure there is also provided a first heat transfer configured to remove heat from the at least one electronic circuitry component, and a second heat transfer configured to remove heat from the at least one photonic component.

A cooling apparatus includes a casing, pumping unit, and heat exchange unit. The pumping unit includes a body and housing. The body includes a wishbone-shaped indentation and lollipop shaped indentation separate from the wishbone-shaped indentation. The housing includes a wishbone-shaped flow path and lollipop-shaped flow path separate from the wishbone-shaped flow path. The body is coupled to the housing such that the wishbone-shaped indentation and the wishbone-shaped flow path define a first flow path and the lollipop-shaped indentation and the lollipop-shaped flow path define a second flow path. The pumping unit is coupled to the heat exchange chamber such that the first flow path and the second flow path is in fluid communication with the heat exchange chamber via a first end opening and second end opening, and third opening, respectively.

A cooling apparatus includes a casing, pumping unit, and heat exchange unit. The pumping unit includes a body and housing. The body includes a wishbone-shaped indentation and lollipop shaped indentation separate from the wishbone-shaped indentation. The housing includes a wishbone-shaped flow path and lollipop-shaped flow path separate from the wishbone-shaped flow path. The body is coupled to the housing such that the wishbone-shaped indentation and the wishbone-shaped flow path define a first flow path and the lollipop-shaped indentation and the lollipop-shaped flow path define a second flow path. The pumping unit is coupled to the heat exchange chamber such that the first flow path and the second flow path is in fluid communication with the heat exchange chamber via a first end opening and second end opening, and third opening, respectively.

A semiconductor package includes an interposer, an electronic device having a first side surface and a second side surface opposite to the first side surface, and including a plurality of memory dies stacked in a vertical direction, at least one first through pipe passing through the electronic device in the vertical direction adjacent to the first side surface, and moving a cooling liquid therein, and a plurality of thermal transmission lines extending in a horizontal direction inside the memory die, and extending in parallel from the first through pipe toward the second side surface.

A semiconductor package includes an interposer, an electronic device having a first side surface and a second side surface opposite to the first side surface, and including a plurality of memory dies stacked in a vertical direction, at least one first through pipe passing through the electronic device in the vertical direction adjacent to the first side surface, and moving a cooling liquid therein, and a plurality of thermal transmission lines extending in a horizontal direction inside the memory die, and extending in parallel from the first through pipe toward the second side surface.

Systems including power device embedded PCBs coupled to cooling devices and methods of forming the same are disclosed. One system includes a power device embedded PCB stack, a cooling assembly including a cold plate having one or more recesses therein, and a buffer cell disposed within each of the one or more recesses. The cooling assembly is bonded to the PCB stack with a insulation substrate disposed therebetween. The cooling assembly is arranged such that the buffer cell faces the PCB stack and absorbs stress generated at an interface of the PCB stack and the cooling assembly.

A cold plate having a copper base plate and a plurality of fins on the copper base plate. The fins are porous and made by 3D printing a copper-silver alloy on the copper base plate. Alternatively, the fins can be 3D printed and then adhered to the copper base plate with a brazing material. The copper base plate is placed on electronics to be cooled, such as a chip package, using a thermal interface material. An optional manifold can be placed on the copper base plate for circulating a coolant across the fins.

A cold plate having a copper base plate and a plurality of fins on the copper base plate. The fins are porous and made by 3D printing a copper-silver alloy on the copper base plate. Alternatively, the fins can be 3D printed and then adhered to the copper base plate with a brazing material. The copper base plate is placed on electronics to be cooled, such as a chip package, using a thermal interface material. An optional manifold can be placed on the copper base plate for circulating a coolant across the fins.

A chip carrier socket for an electronic-photonic integrated-circuit (EPIC) assembly comprises a carrier bottom and a carrier top configured to mate to the carrier bottom while enclosing the EPIC assembly within an enclosed cavity. The carrier bottom comprises one or more conductive vias passing from a first surface of the carrier bottom to an opposite second surface of the carrier bottom, each conductive via providing electrical connectivity between an electrically conductive pad on the first surface of the carrier bottom and a respective electrically conductive pad, solder ball, or electrically conductive spring on the second surface of the carrier bottom. One or both of the carrier bottom and the carrier top comprises a fluid inlet port and a fluid outlet port. Further, either or both of the carrier bottom and the bottom top comprises an optical via passing from one surface to another of the carrier bottom or carrier top.

A chip carrier socket for an electronic-photonic integrated-circuit (EPIC) assembly comprises a carrier bottom and a carrier top configured to mate to the carrier bottom while enclosing the EPIC assembly within an enclosed cavity. The carrier bottom comprises one or more conductive vias passing from a first surface of the carrier bottom to an opposite second surface of the carrier bottom, each conductive via providing electrical connectivity between an electrically conductive pad on the first surface of the carrier bottom and a respective electrically conductive pad, solder ball, or electrically conductive spring on the second surface of the carrier bottom. One or both of the carrier bottom and the carrier top comprises a fluid inlet port and a fluid outlet port. Further, either or both of the carrier bottom and the bottom top comprises an optical via passing from one surface to another of the carrier bottom or carrier top.