A photonic integrated circuit device includes a semiconductor substrate (e.g., wafer) having a chip region therein, which is bounded on at least one side thereof by a scribe line. The chip region includes an optical transmitter, an optical receiver and a test optical waveguide. This test optical waveguide is coupled to the optical transmitter and the optical receiver and overlaps the scribe line. During a substrate dicing operation, a portion of the test optical waveguide overlapping the scribe line is removed.

Novel connection between neurons of a neural network is provided. A perceptron included in the neural network includes a plurality of neurons; the neuron includes a synapse circuit and an activation function circuit; and the synapse circuit includes a plurality of memory cells. A bit line selected by address information for selecting a memory cell is shared by a plurality of perceptrons. The memory cell is supplied with a weight coefficient of an analog signal, and the synapse circuit is supplied with an input signal. The memory cell multiplies the input signal by the weight coefficient and converts the multiplied result into a first current. The synapse circuit generates a second current by adding a plurality of first currents and converts the second current into a first potential. The activation function circuit is a semiconductor device that converts the first potential into a second potential by a ramp function and supplies the second potential as an input signal of the synapse circuit included in the perceptron in a next stage.

Disclosed is an amplifying circuit and method. In one embodiment, an amplifying circuit, includes: a common-gate (CG) amplifier, wherein the CG amplifier comprises a first transistor, wherein source terminal and body terminal of the first transistor is coupled together through a first resistor.

An integrated circuit includes a resistive material layer formed on a substrate, a metal layer formed on the resistive material layer, a bipolar transistor formed on the substrate, and a resistive element formed on the substrate. The bipolar transistor includes, as a sub-layer, the metal layer formed in a first region, and also includes a collector layer formed on the sub-collector layer. The resistive element is constituted by the resistive material layer formed in a second region.

A 3D-IC includes a first tier device and a second tier device. The first tier device and the second tier device are vertically stacked together. The first tier device includes a first substrate and a first interconnect structure formed over the first substrate. The second tier device includes a second substrate, a doped region formed in the second substrate, a dummy gate formed over the substrate, and a second interconnect structure formed over the second substrate. The 3D-IC also includes an inter-tier via extends vertically through the second substrate. The inter-tier via has a first end and a second end opposite the first end. The first end of the inter-tier via is coupled to the first interconnect structure. The second end of the inter-tier via is coupled to one of: the doped region, the dummy gate, or the second interconnect structure.

Embodiments of a marking pattern in forming the staircase structure of a three-dimensional (3D) memory device are provided. In an example, a semiconductor device includes a stack structure having insulating layers and conductor layers arranged alternatingly over a substrate along a vertical direction; and a marking pattern having interleaved layers over the substrate and neighboring the stack structure. The marking pattern includes a central marking structure located in a marking area. The central marking structure consists of interleaved layers and divides the marking area into a first marking sub-area and a second marking sub-area. A first pattern density of the first marking sub-area is higher than or equal to a second pattern density of the second marking sub-area.

In an embodiment, a semiconductor device is provided that includes a main transistor having a load path, a sense transistor configured to sense a main current flowing in the load path of the main transistor, and at least one bypass diode structure configured to protect the sense transistor. The at least one bypass diode structure is electrically coupled in parallel with the sense transistor.

A 3D semiconductor device including: a first level including a single crystal silicon layer and a plurality of first transistors, the plurality of first transistors each including a single crystal channel; a first metal layer overlaying the plurality of first transistors; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; a second level is disposed above the third metal layer, where the second level includes a plurality of second transistors; a fourth metal layer disposed above the second level; and a connective path between the fourth metal layer and either the third metal layer or the second metal layer, where the connective path includes a via disposed through the second level, where the via has a diameter of less than 800 nm and greater than 5 nm, and where at least one of the plurality of second transistors includes a metal gate.

A semiconductor device includes first and second chips that are stacked such that first surfaces of their element layers face each other. Each chip has a substrate, an element layer on a first surface of the substrate, pads on the element layer, and vias that penetrate through the substrate and the element layer. Each via is exposed from a second surface of the substrate and directly connected to one of the pads. The vias include a first via of the first chip directly connected to a first pad of the first chip and a second via of the second chip directly connected to a second pad of the second chip. The pads further include a third pad of the second chip which is electrically connected to the second pad by a wiring in the element layer of the second chip and to the first pad through a micro-bump.

A device area and a marking area neighboring the device area over a dielectric stack are determined. The dielectric stack includes insulating material layers and sacrificial material layers arranged alternatingly over a substrate. The device area and the marking area are patterned using a same etching process to form a marking pattern having a central marking structure in a marking area and a staircase pattern in the device area. The marking pattern and the staircase pattern have a same thickness equal to a thickness of at least one insulating material layer and one sacrificial material layer, and the central marking structure divides the marking area into a first marking sub-area farther from the device area and a second marking sub-area closer to the device area. A first pattern density of the first marking sub-area is greater than or equal to a second pattern density of the second marking sub-area. A photoresist layer is formed to cover the staircase pattern and expose the marking pattern, and the photoresist layer is trimmed to expose a portion of the dielectric stack along a horizontal direction. An etching process is performed to maintain the marking pattern and remove the exposed portion of the dielectric stack and form a staircase.