A bias current generator circuit includes a current path and a leakage control circuit. The current path is connected between a supply voltage and a ground level. The current path includes a transistor and a resistor. The transistor has a current channel connected in the current path. The resistor has an upper terminal and a lower terminal connected in the current path, and a well contact to allow a reverse leakage current of the resistor to flow through. The leakage control circuit is connected to the supply voltage. The leakage control circuit includes a driving transistor to provide a driving voltage to the well contact of the resistor, and to allow the reverse leakage current of the resistor to flow into the leakage control circuit.

A semiconductor device includes a JFET and a MOSFET cascode-connected to each other such that a source electrode of the JFET is connected to a drain electrode of the MOSFET. The JFET is configured such that a breakdown voltage between a gate layer and a body layer is set lower than a breakdown voltage of the MOSFET.

Provided is a semiconductor device comprising: a semiconductor substrate; a gate trench section that is provided from an upper surface to an inside of the semiconductor substrate and extends in a predetermined extending direction on the upper surface of the semiconductor substrate; a mesa section in contact to the gate trench section in an arrangement direction orthogonal the extending direction; and an interlayer dielectric film provided above the semiconductor substrate; wherein the interlayer dielectric film is provided above at least a part of the gate trench section in the arrangement direction; a contact hole through which the mesa section is exposed is provided to the interlayer dielectric film; and a width of the contact hole in the arrangement direction is equal to or greater than a width of the mesa section in the arrangement direction.

A stacked three dimensional semiconductor device includes multiple thin substrates stacked over one another and over a base substrate. The thin substrates may include a thickness of about 0.1 μm. In some embodiments, a noise suppression tier is vertically interposed between active device tiers. In some embodiments, each tier includes active device portions and noise suppression portions and the tiers are arranged such that noise suppression portions are vertically interposed between active device portions. The noise suppression portions include decoupling capacitors in a power/ground mesh and alleviate vertical noise.

An object of one embodiment of the present invention is to propose a memory device in which a period in which data is held is ensured and memory capacity per unit area can be increased. In the memory device of one embodiment of the present invention, bit lines are divided into groups, and word lines are also divided into groups. The word lines assigned to one group are connected to the memory cell connected to the bit lines assigned to the one group. Further, the driving of each group of bit lines is controlled by a dedicated bit line driver circuit of a plurality of bit line driver circuits. In addition, cell arrays are formed on a driver circuit including the above plurality of bit line driver circuits and a word line driver circuit. The driver circuit and the cell arrays overlap each other.

A method includes forming a transistor having source and drain regions. The following are formed on the source/drain region: a first via, a first metal layer extending along a first direction on the first via, a second via overlapping the first via on the first metal layer, and a second metal extending along a second direction different from the first direction on the second via; and the following are formed on the drain/source region: a third via, a third metal layer on the third via, a fourth via overlapping the third via over the third metal layer, and a controlled device at a same height level as the second metal layer on the third metal layer.

Techniques regarding anchors for fins comprised within stacked VTFET devices are provided. For example, one or more embodiments described herein can comprise an apparatus, which can further comprise a fin extending from a semiconductor body. The fin can be comprised within a stacked vertical transport field effect transistor device. The apparatus can also comprise a dielectric anchor extending from the semiconductor body and adjacent to the fin. Further, the dielectric anchor can be coupled to the fin.

A resistor includes a substrate including an active region protruding from an upper surface of the substrate and extending in a first horizontal direction, a doped region extending in the first horizontal direction on the active region and comprising a semiconductor layer with n-type impurities, a plurality of channel layers spaced apart from each other in a vertical direction on the active region and connected to the doped region, a first gate electrode and a second gate electrode extending in the second horizontal direction intersecting the first horizontal direction and surrounding the plurality of channel layers, a first contact plug and a second contact plug in contact with an upper surface of the doped region. The first contact plug is adjacent to the first gate electrode. The second contact plug is adjacent to the second gate electrode.

Gallium nitride-based monolithic microwave integrated circuits (MMICs) can comprise aluminum-based metals. Electrical contacts for gates, sources, and drains of transistors can include aluminum-containing metallic materials. Additionally, connectors, inductors, and interconnect devices can also comprise aluminum-based metals. The gallium-based MMICs can be manufactured in complementary metal oxide semiconductor (CMOS) facilities with equipment that produces silicon-based semiconductor devices.

The present disclosure relates to thin-form-factor reconstituted substrates and methods for forming the same. The reconstituted substrates described herein may be utilized to fabricate homogeneous or heterogeneous high-density 3D integrated devices. In one embodiment, a silicon substrate is structured by direct laser patterning to include one or more cavities and one or more vias. One or more semiconductor dies of the same or different types may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. One or more conductive interconnections are formed in the vias and may have contact points redistributed to desired surfaces of the reconstituted substrate. The reconstituted substrate may thereafter be integrated into a stacked 3D device.