A semiconductor device in which a transistor and a diode are formed on a common semiconductor substrate is provided. The semiconductor substrate includes a transistor region in which a transistor is formed and a diode region in which a diode is formed. At least one first electrode on a second main surface side of the transistor region and at least one second electrode on a second main surface side of the diode region are made of different materials.

Methods and apparatus to form silicon-based transistors on group III-nitride materials using aspect ratio trapping are disclosed. An example integrated circuit includes a group III-nitride substrate and a fin of silicon formed on the group III-nitride substrate. The integrated circuit further includes a first transistor formed on the fin of silicon and a second transistor formed on the group III-nitride substrate.

The invention relates to a silicon-based multifunction substrate. The silicon-based multifunction substrate comprises bulk silicon regions extending from a front surface to a back surface of the silicon-based multifunction substrate and at least one buried oxide layer laterally arranged between the bulk silicon regions. The buried oxide layer is covered by a structured silicon layer extending up to the front surface. The structured silicon layer comprises, laterally arranged between the bulk silicon regions, at least two silicon-on-insulator regions, herein SOI regions, with different thicknesses above the buried oxide layer. The SOI regions of the structured silicon layer are electrically insulated from each other by a respective first trench isolation extending from the front surface to the buried oxide layer.

Power semiconductor devices comprise a wide bandgap semiconductor layer structure, a gate pad on the wide bandgap semiconductor layer structure, a plurality of gate fingers on the wide bandgap semiconductor layer structure, and a plurality of lumped gate resistors electrically coupled between the gate pad and the gate fingers.

A method may include forming a first atomic layer deposition (ALD) bonding layer on a surface of a first semiconductor device, and forming a second ALD bonding layer on a surface of a second semiconductor device. The method may include joining the first semiconductor device and the second semiconductor device via the first ALD bonding layer and the second ALD bonding layer. The method may include performing an annealing operation to fuse the first ALD bonding layer and the second ALD bonding layer and form a single ALD bonding layer that bonds the first semiconductor device with the second semiconductor device.

All of four of built-in gate resistance trenches function as practical built-in gate resistance trenches. A first end portion of each of four of the built-in gate resistance trenches is electrically connected to a wiring side contact region of a gate wiring via a wiring contact. A second end portion of each of four of the built-in gate resistance trenches is electrically connected to a pad side contact region of a gate pad via a pad contact. In each of four of the built-in gate resistance trenches, a distance between the wiring contact and the pad contact is defined as an inter-contact distance.

Power semiconductor devices comprise a gate pad, a plurality of gate fingers, and a first gate resistor and a first switch that are coupled between the gate pad and the gate fingers.

A semiconductor device includes a main element and a sense element. Each of the main element and the sense element includes a drift layer, a base layer, an emitter region, a gate insulation film, a gate electrode, and a rear surface layer. The base layer is on the drift layer. The emitter region is at a surface layer portion of the base layer. The gate insulation film is disposed at a surface of the base layer between the emitter region and the drift layer. The gate electrode is on the gate insulation film. The rear surface layer faces the base layer with the drift layer between the rear surface layer and the base layer. The rear surface layer in the main element includes a collector layer. The rear surface layer in the sense element includes a low-impurity layer having smaller amount of impurities than the collector layer.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A first isolation structure separates a first end of a first portion of the fin from a first end of a second portion of the fin, the first end of the first portion of the fin having a depth. A gate structure is over the top of and laterally adjacent to the sidewalls of a region of the first portion of the fin. A second isolation structure is over a second end of a first portion of the fin, the second end of the first portion of the fin having a depth different than the depth of the first end of the first portion of the fin.

A semiconductor device includes a substrate, a first well region, a second well region, an isolation region, a first resistor segment and a second resistor segment. The substrate includes a region having a first conductivity type. The first and the second well regions are disposed in the region of the substrate. The isolation region is disposed on the first and the second well regions. The first and the second resistor segments are electrically connected to each other and disposed on the isolation region. Moreover, the first and the second well regions are disposed directly under the first and the second resistor segments, respectively. The first and the second well regions do not overlap with each other in a vertical projection direction and have a second conductivity type that is opposite to the first conductivity type.