A pixel electrode or a common electrode is a light-transmissive conductive film; therefore, it is formed of ITO conventionally. Accordingly, the number of manufacturing steps and masks, and manufacturing cost have been increased. An object of the present invention is to provide a semiconductor device, a liquid crystal display device, and an electronic appliance each having a wide viewing angle, less numbers of manufacturing steps and masks, and low manufacturing cost compared with a conventional device. A semiconductor layer of a transistor, a pixel electrode, and a common electrode of a liquid crystal element are formed in the same step.

The present invention aims to reduce a failure in a fuel cell module and reduce manufacturing costs by specifying and taking countermeasures against cells in short-circuit failure from among fuel cells manufactured on a substrate by using a thin-film deposition process. In a fuel cell array according to the present invention, each fuel cell includes a solid electrolyte layer between a first electrode layer and a second electrode layer. A first wiring is connected to the second electrode layer, and a second wiring is connected to the first electrode layer through a connection element. The connection element is formed by sandwiching a conductive layer between two electrodes (refer to FIG. 8).

A display panel and a display device are provided. The display panel has a display area including a conventional display region and a translucent display region; and a non-display area. First sub-pixels, second sub-pixels and third sub-pixels are provided in the conventional display region, the first sub-pixels are arranged in a first density, and the second and third sub-pixels are arranged in a second density. Fourth sub-pixels, fifth sub-pixels and sixth sub-pixels are provided in the translucent display region, the fourth sub-pixel has a same color as the first sub-pixel, the fifth sub-pixel has a same color as the second sub-pixel, and the sixth sub-pixel has a same color as the third sub-pixel. The fourth sub-pixels are arranged in a third density equal to the first density, the fifth and sixth sub-pixels are arranged in a fourth density. The second density is greater than the fourth density.

A 3D semiconductor device including: a first level including a plurality of first single-crystal transistors; a plurality of memory control circuits formed from at least a portion of the plurality of first single-crystal transistors; a first metal layer disposed atop the plurality of first single-crystal transistors; a second metal layer disposed atop the first metal layer; a second level disposed atop the second metal layer, the second level including a plurality of second transistors; a third level including a plurality of third transistors, where the third level is disposed above the second level; a third metal layer disposed above the third level; and a fourth metal layer disposed above the third metal layer, where the plurality of second transistors are aligned to the plurality of first single crystal transistors with less than 140 nm alignment error, the second level includes first memory cells, the third level includes second memory cells.

A flat panel substrate with integrated antennas and wireless power transmission system for delivering power to a receiving device is presented herein. A method can comprise depositing, onto a flat panel substrate, an antenna layer comprising multiple adaptively phased antennas elements; and depositing, onto the flat panel substrate, respective thin film transistor (TFT)-based antenna management circuits for the multiple adaptively phased antenna elements—the respective TFT-based antenna management circuits being operable to measure respective first phases at which first signals are received at the multiple adaptively phased antenna elements, and based on the respective first phases, control respective second phases at which second signals are transmitted from the multiple adaptively phased antenna elements to facilitate delivery, via the second signals, of power to the receiving device. Further, the method comprises forming traces communicatively coupling the multiple adaptively phased antenna elements to the respective TFT-based antenna management circuits.

A thin film transistor array substrate for a digital X-ray detector device including a base substrate; a plurality of data lines and a plurality of gate lines disposed on the base substrate and arranged to cross each other; a driving thin film transistor disposed above the base substrate and including a first electrode, a second electrode, a gate electrode and an active layer; a PIN diode connected to the driving thin film transistor; and at least one shielding layers disposed above the driving thin film transistor and configured to overlay the active layer, wherein the at least one shielding layers are electrically connected to the plurality of data lines.

Provided are an array substrate and a fabrication method therefor, a shift register unit, and a display panel. The array substrate includes a first transistor having a double gate structure, and further includes an active layer arranged on one side of the base substrate and a first conductive layer. The active layer includes a first conductor portion connected between a first semiconductor portion and a second semiconductor portion, the first semiconductor portion and a second semiconductor portion forming a channel region of the first transistor. The first conductive layer includes a first conductive portion connected to a stable voltage source, an orthographic projection of the first conductive portion on the base substrate at least partially overlaps with an orthographic projection of the first conductor portion on the base substrate, and the first conducting portion and the first conductor portion form two electrodes of a parallel-plate capacitor.

A display device includes a substrate; a semiconductor layer disposed on the substrate; a gate insulating film disposed on the semiconductor layer; a gate layer disposed on the gate insulating film and insulated from the semiconductor layer; an insulating film disposed on the semiconductor layer and the gate layer; and a metal layer disposed on the insulating film, wherein the semiconductor layer and the gate layer are electrically connected through the metal layer, and the semiconductor layer overlaps the gate layer in a plan view.

A display apparatus includes: a display panel; a driving circuit which provides a driving signal to the display panel and includes at least one driving transistor; and a clock signal wiring for providing a clock signal to the driving circuit. The driving circuit includes an active pattern, a gate pattern, a source pattern, and a shielding pattern, the gate pattern overlaps the active pattern in a plan view, a major surface plane of the source pattern is disposed in a layer different from a layer the active pattern is disposed in, the source pattern is electrically connected to the active pattern, the shielding pattern is disposed between the gate pattern and the clock signal wiring and applied with a constant voltage, and the clock signal wiring overlaps the gate pattern in the plan view and is disposed on the source pattern.

In an embodiment an arrangement includes a plurality of pixels, wherein each pixel includes at least two subpixels of each color, wherein each color is defined by a predefined target color location, wherein each subpixel comprises an optoelectronic component defined by a color location, wherein the color locations of the optoelectronic components of each color is chosen such that during operation of the optoelectronic components the predefined target color location is met for each color, wherein the optoelectronic components for each color are of identical design, and a controller configured to commonly control the optoelectronic components of a color.