When a conductive layer occupying a large area is provided in a coiled antenna portion, it has been difficult to supply power stably. A memory circuit portion and a coiled antenna portion are disposed by being stacked together; therefore, it is possible to prevent a current from flowing through a conductive layer occupying a large area included in the memory circuit portion, and thus, power saving can be achieved. In addition, the memory circuit portion and the coiled antenna portion are disposed by being stacked together, and thus, it is possible to use a space efficiently. Therefore, downsizing can be realized.

When a conductive layer occupying a large area is provided in a coiled antenna portion, it has been difficult to supply power stably. A memory circuit portion and a coiled antenna portion are disposed by being stacked together; therefore, it is possible to prevent a current from flowing through a conductive layer occupying a large area included in the memory circuit portion, and thus, power saving can be achieved. In addition, the memory circuit portion and the coiled antenna portion are disposed by being stacked together, and thus, it is possible to use a space efficiently. Therefore, downsizing can be realized.

A capacitor includes a semiconductor substrate. The capacitor also includes a first terminal having a fin disposed on a surface of the semiconductor substrate. The capacitor further includes a dielectric layer disposed onto the fin. The capacitor still further includes a second terminal having a FinFET compatible high-K metal gate disposed proximate and adjacent to the fin.

A capacitor includes a semiconductor substrate. The capacitor also includes a first terminal having a fin disposed on a surface of the semiconductor substrate. The capacitor further includes a dielectric layer disposed onto the fin. The capacitor still further includes a second terminal having a FinFET compatible high-K metal gate disposed proximate and adjacent to the fin.

A method, apparatus, and system for protection from hazards of conductivity is disclosed using non-electrical means to disrupt electrical current with a thermovolumetric substance. The purpose of this invention is to prevent hazardous conditions from occurring by disrupting the flow of electrical current prior to the development of arc fault conditions.

This disclosure provides an array substrate and a method of manufacturing the same. The method includes: forming a switch element; etching on an extension of a gate insulation layer to obtain a second amorphous silicon layer, a second N-type amorphous silicon layer and a light sensing metal at the same time to form a photosensor; forming a light sensing layer and a passivation layer on a source metal, a drain metal, and the light sensing metal; and forming a first light sensing layer and a first passivation layer on the source metal and the drain metal, and forming a second light sensing layer and a second passivation layer on the light sensing metal by using a second mask.

Producing a semiconductor or piezoelectric on-insulator type substrate for RF applications which is provided with a porous layer under the BOX layer and under a layer of polycrystalline semiconductor material.

A semiconductor device is provided; the semiconductor device includes unipolar transistors. A steady-state current does not flow in the semiconductor device. The semiconductor device uses a high-level potential and a low-level potential to express a high level and a low level, respectively. The semiconductor device includes unipolar transistors, a capacitor, first and second input terminals, and an output terminal. To the second input terminal, a signal is input whose logic is inverted from the logic of a signal input to the first input terminal. The semiconductor device has a circuit structure called bootstrap in which two unipolar transistors are connected in series between the high-level potential and the low-level potential and a capacitor is provided between an output terminal and a gate of one of the two transistors. A delay is caused between the gate of the transistor and the signal output from the output terminal, whereby the bootstrap can be certainly performed.

There is disclosed herein an SOI IC comprising an integrated capacitor comprising a parallel arrangement of a metal-insulator-metal, MIM, capacitor, a second capacitor, a third capacitor, and a fourth capacitor:

wherein the second capacitor comprises as plates the substrate and a one of a plurality of semiconductor layers having an n-type doping, and comprises the buried oxide layer as dielectric;
the third capacitor comprises as plates the polysilicon layer and a further one of a plurality of semiconductor layers having an n-type doping, and comprises an insulating layer between the plurality of semiconductor layers and the metallisation stack as dielectric; and
the fourth capacitor comprises as plates the polysilicon plug and at least one of the plurality of semiconductor layers and comprises the oxide-lining as dielectric, wherein the oxide lining and the polysilicon plug form part of a lateral isolation (DTI) structure.

There is disclosed herein an SOI IC comprising an integrated capacitor comprising a parallel arrangement of a metal-insulator-metal, MIM, capacitor, a second capacitor, a third capacitor, and a fourth capacitor:

wherein the second capacitor comprises as plates the substrate and a one of a plurality of semiconductor layers having an n-type doping, and comprises the buried oxide layer as dielectric;
the third capacitor comprises as plates the polysilicon layer and a further one of a plurality of semiconductor layers having an n-type doping, and comprises an insulating layer between the plurality of semiconductor layers and the metallisation stack as dielectric; and
the fourth capacitor comprises as plates the polysilicon plug and at least one of the plurality of semiconductor layers and comprises the oxide-lining as dielectric, wherein the oxide lining and the polysilicon plug form part of a lateral isolation (DTI) structure.