A C-plane GaN substrate only mildly restricts the shape and dimension of a nitride semiconductor device formed on the substrate. The variation of an off-angle on the main surface of the substrate is suppressed. In the C-plane GaN substrate: the substrate comprises a plurality of facet growth areas each having a closed ring outline-shape on the main surface; the number density of the facet growth area accompanied by a core among the plurality of facet growth areas is less than 5 cm.sup.−2 on the main surface; and, when any circular area of 4 cm diameter is selected from an area which is on the main surface and is distant by 5 mm or more from the outer peripheral edge of the substrate, the variation widths of an a-axis direction component and an m-axis direction component of an off-angle within the circular area is each 0.25 degrees or less.

According to one embodiment, a semiconductor device includes first to third electrodes, first and second semiconductor regions, and a first member. The first semiconductor region includes Al.sub.x1Ga.sub.1-x1N (0≤x1<1). The second semiconductor region includes Al.sub.x2Ga.sub.1-x2N (x1<x2≤1). The first member includes first and second regions. The second region is between the first region and the first electrode region of the second electrode. A part of the second region is between the second semiconductor portion of the second semiconductor region and the second electrode region. The second region includes at least one first element selected from the group consisting of Ti, Al, Ga, Ni, Nb, Mo, Ta, Hf, V, and Au. The first region does not include the first element, or a concentration of the first element in the first region is lower than a concentration of the first element in the second region.

A semiconductor device includes a semiconductor body, an electrode provided on a surface of the semiconductor body. The semiconductor body includes a first semiconductor layer and a second semiconductor layer provided between the first semiconductor layer and the second electrode. The second semiconductor layer includes first and second regions arranged along the surface of the semiconductor body. The first region has a surface contacting the electrode, and the second region includes second conductivity type impurities with a concentration lower than a concentration of the second conductivity type impurities at the surface of the first region. The second semiconductor layer has a first concentration of second conductivity type impurities at a first position in the second region, and a second concentration of second conductivity type impurities at a second position between the first position and the electrode, the second concentration being lower than the first concentration.

An electrical device includes a counterdoped heterojunction selected from a group consisting of a pn junction or a p-i-n junction. The counterdoped junction includes a first semiconductor doped with one or more n-type primary dopant species and a second semiconductor doped with one or more p-type primary dopant species. The device also includes a first counterdoped component selected from a group consisting of the first semiconductor and the second semiconductor. The first counterdoped component is counterdoped with one or more counterdopant species that have a polarity opposite to the polarity of the primary dopant included in the first counterdoped component. Additionally, a level of the n-type primary dopant, p-type primary dopant, and the one or more counterdopant is selected to the counterdoped heterojunction provides amplification by a phonon assisted mechanism and the amplification has an onset voltage less than 1 V.

It is an object of the present invention to enhance connection reliability of terminals while enhancing assembling performance. A power conversion device according to the present invention includes: a power semiconductor module having a power terminal; a capacitor module for supplying smoothed power to the power semiconductor module; and a mold bus bar in which a conductor part for electrically connecting the power semiconductor module and the capacitor module is sealed by a resin material, wherein the capacitor module has a positive capacitor terminal and a negative capacitor terminal, the power terminal, the positive capacitor terminal, and the negative capacitor terminal are formed such that the main surfaces of the terminals face in the same direction, and the mold bus bar has a first terminal contacting with the main surface of the power terminal, a second terminal contacting with the main surface of the positive capacitor terminal, and a third terminal contacting with the main surface of the negative capacitor terminal.

A bipolar semiconductor device includes at least a four-layer structure, a first main side with a first electrical contact, and a second main side with a second electrical contact separated from the first main side by at least a base layer of first conductivity type. A shorting layer of the first conductivity type is arranged on the second main side of the base layer. A third layer includes a patterned highly conductive material, such as metal and/or silicides, graphene, etc., and is deposited on the shorting. A fourth layer of the second conductivity type is arranged directly on the third layer, inserted between the shorting layer and the second electrical contact. This concept can be applied to any non-punch-through or punch-through reverse conducting IGBT designs, but is particularly effective for devices using thin wafers, and is also applicable to bipolar diodes in order to improve a soft recovery process.

A semiconductor device includes an N-type drift layer provided between a first main surface and a second main surface of the semiconductor substrate and an N-type buffer layer provided between the N-type drift layer and the first main surface and having a higher impurity peak concentration than the N-type drift layer. The N-type buffer layer has a structure that a first buffer layer, a second buffer layer, a third buffer layer, and a fourth buffer layer are disposed in this order from a side of the first main surface. When a distance from an impurity peak position of the first buffer layer to an impurity peak position of the second buffer layer is L12 and a distance from an impurity peak position of the second buffer layer to an impurity peak position of the third buffer layer is L23, a relationship of L23/L12≥3.5 is satisfied.

There are provided a transistor including a first semiconductor layer of a first conductivity type, a second semiconductor layer thereabove, a first impurity region of a second conductivity type provided in an upper layer part of the second semiconductor layer, a second impurity region of a first conductivity type provided in an upper layer part of the first impurity region, a gate electrode facing the first impurity region and the second semiconductor layer with a gate insulating film interposed in between, and first and second main electrodes; a parasitic transistor with the second impurity region as a collector, the first and the second semiconductor layers as an emitter, and the first impurity region as a base; a parasitic diode with the first impurity region as an anode, and the first and the second semiconductor layers as a cathode; and a pn junction diode with the first impurity region as an anode, and the second impurity region as a cathode.

Some embodiments of the present disclosure provide a semiconductor device, including a substrate, a channel layer, a barrier layer, a p-type doped III-V layer, a source, a drain and a doped semiconductor layer. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The p-type doped III-V layer is disposed on the barrier layer. A gate is disposed on the p-type doped III-V layer. The source and the drain are arranged on two opposite sides of the gate. The doped semiconductor layer is provided with a first side close to the gate and a second side away from the gate. The drain covers the first side of the doped semiconductor layer.

Disclosed are a semiconductor structure and a preparation method therefor. The semiconductor structure includes: a substrate, a channel layer, a barrier layer, a gate structure, a source, and a drain, where the gate structure includes a p-type semiconductor layer, an n-type semiconductor layer, and a gate. In this way, a control capability of a gate to a channel is improved; a threshold voltage of a semiconductor device is improved, avoiding vertical electric leakage of a gate structure, and reducing side electric leakage of the gate structure; and channel degradation is avoided, improving overall output characteristics of the device.