SEMICONDUCTOR DEVICE

Abstract

A semiconductor device includes an N-type drift layer provided between a first main surface and a second main surface of the semiconductor substrate and an N-type buffer layer provided between the N-type drift layer and the first main surface and having a higher impurity peak concentration than the N-type drift layer. The N-type buffer layer has a structure that a first buffer layer, a second buffer layer, a third buffer layer, and a fourth buffer layer are disposed in this order from a side of the first main surface. When a distance from an impurity peak position of the first buffer layer to an impurity peak position of the second buffer layer is L12 and a distance from an impurity peak position of the second buffer layer to an impurity peak position of the third buffer layer is L23, a relationship of L23/L12≥3.5 is satisfied.

Claims

1. A semiconductor device, comprising: a drift layer of a first conductivity type provided between a first main surface and a second main surface of a semiconductor substrate; and a buffer layer of a first conductivity type provided between the drift layer and the first main surface and having a higher impurity peak concentration than the drift layer, wherein the buffer layer has a structure that a first buffer layer, a second buffer layer, a third buffer layer, and a fourth buffer layer are disposed in this order from a side of the first main surface, and when a distance from an impurity peak position of the first buffer layer to an impurity peak position of the second buffer layer is L12 and a distance from an impurity peak position of the second buffer layer to an impurity peak position of the third buffer layer is L23, a relationship of L23/L12≥3.5 is satisfied.

2. The semiconductor device according to claim 1, wherein an impurity constituting the first buffer layer is phosphorus, and an impurity constituting the second buffer layer, the third buffer layer, and the fourth buffer layer is proton.

3. The semiconductor device according to claim 1, wherein when the impurity peak concentration of the second buffer layer is C2, the impurity peak concentration of the third buffer layer is C3, and the impurity peak concentration of the fourth buffer layer is C4, a relationship of C2>C3>C4 is satisfied.

4. The semiconductor device according to claim 1, wherein the impurity peak concentration of each of the second buffer layer, the third buffer layer, and the fourth buffer layer is equal to or smaller than 2.0×10.sup.15/cm.sup.3.

5. The semiconductor device according to claim 1, wherein when a distance from an impurity peak position of the third buffer layer to an impurity peak position of the fourth buffer layer is L34, a relationship of L23/L34>1 is satisfied.

6. The semiconductor device according to claim 1, wherein withstand voltage is equal to or smaller than 750V, a specific resistance of the drift layer is equal to or larger than 20 Ω.Math.cm and equal to or smaller than 40 Ω.Math.cm, and a sum of a thickness of the drift layer and a thickness of the buffer layer is equal to or larger than 50 μm and equal to or smaller than 80 μm.

7. The semiconductor device according to claim 1, wherein withstand voltage is 1200V, a specific resistance of the drift layer is equal to or larger than 50 Ω.Math.cm and equal to or smaller than 90 Ω.Math.cm, and a sum of a thickness of the drift layer and a thickness of the buffer layer is equal to or larger than 100 μm and equal to or smaller than 130 μm.

8. The semiconductor device according to claim 1, wherein withstand voltage is 1700V, a specific resistance of the drift layer is equal to or larger than 90 Ω.Math.cm and equal to or smaller than 130 Ω.Math.cm, and a sum of a thickness of the drift layer and a thickness of the buffer layer is equal to or larger than 170 μm and equal to or smaller than 210 μm.

9. The semiconductor device according to claim 1, wherein withstand voltage is 2000V, a specific resistance of the drift layer is equal to or larger than 130 Ω.Math.cm and equal to or smaller than 180 Ω.Math.cm, and a sum of a thickness of the drift layer and a thickness of the buffer layer is equal to or larger than 200 μm and equal to or smaller than 260 μm.

10. The semiconductor device according to claim 1, wherein withstand voltage is 3300V, a specific resistance of the drift layer is equal to or larger than 200 Ω.Math.cm and equal to or smaller than 350 Ω.Math.cm, and a sum of a thickness of the drift layer and a thickness of the buffer layer is equal to or larger than 340 μm and equal to or smaller than 420 μm.

11. The semiconductor device according to claim 1, wherein withstand voltage is 4500V, a specific resistance of the drift layer is equal to or larger than 300 Ω.Math.cm and equal to or smaller than 450 Ω.Math.cm, and a sum of a thickness of the drift layer and a thickness of the buffer layer is equal to or larger than 420 μm and equal to or smaller than 540 μm.

12. The semiconductor device according to claim 1, wherein withstand voltage is 6500V, a specific resistance of the drift layer is equal to or larger than 600 Ω.Math.cm and equal to or smaller than 900 Ω.Math.cm, and a sum of a thickness of the drift layer and a thickness of the buffer layer is equal to or larger than 580 μm and equal to or smaller than 720 μm.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIG. 1 is a cross-sectional view of a major part of an IGBT according to an embodiment 1.

[0009] FIG. 2 is a drawing illustrating a profile of an impurity concentration near a rear surface of a semiconductor substrate in the IGBT according to the embodiment 1.

[0010] FIG. 3 is a drawing illustrating a profile of an impurity concentration near rear surfaces of semiconductor substrates in three IGBTs on which a simulation has been performed.

[0011] FIG. 4 is a drawing illustrating a relationship between a depth of a second buffer layer and current which can be controlled in an RBSOA.

[0012] FIG. 5 is a drawing illustrating a result of a simulation of a waveform of emitter-collector voltage at a time of turn off of the IGBT in which an N-type buffer layer is made up of only a first buffer layer.

[0013] FIG. 6 is a drawing illustrating a result of a simulation of emitter-collector voltage at the time of turn off of the three IGBTs on which the simulation has been performed.

[0014] FIG. 7 is a drawing of enlarging part of FIG. 6.

[0015] FIG. 8 is a drawing illustrating a relationship between L23/L12 and ΔVcep of the IGBT according to the embodiment 1.

[0016] FIG. 9 is a drawing illustrating a relationship between L23/L34 and ΔVcep of the IGBT according to the embodiment 1.

[0017] FIG. 10 is a drawing of a process of manufacturing the IGBT according to the embodiment 1.

[0018] FIG. 11 is a drawing of a process of manufacturing the IGBT according to the embodiment 1.

[0019] FIG. 12 is a drawing of a process of manufacturing the IGBT according to the embodiment 1.

[0020] FIG. 13 is a drawing of a process of manufacturing the IGBT according to the embodiment 1.

[0021] FIG. 14 is a drawing of a process of manufacturing the IGBT according to the embodiment 1.

[0022] FIG. 15 is a drawing of a process of manufacturing the IGBT according to the embodiment 1.

[0023] FIG. 16 is a drawing of a process of manufacturing the IGBT according to the embodiment 1.

[0024] FIG. 17 is a drawing of a process of manufacturing the IGBT according to the embodiment 1.

[0025] FIG. 18 is a drawing of a process of manufacturing the IGBT according to the embodiment 1.

[0026] FIG. 19 is a cross-sectional view of a major part of a diode according to an embodiment 2.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiment 1

[0027] FIG. 1 is a cross-sectional view of a major part of an IGBT which is a semiconductor device according to the embodiment 1. In the present embodiment, an IGBT of 1200 V withstand voltage class is described as an example the IGBT. In the description hereinafter, a first conductivity type is an N type and a second conductivity type is a P type.

[0028] As illustrated in FIG. 1, the IGBT is formed using a semiconductor substrate 20. General silicone may be applied to a material of the semiconductor substrate 20, or wideband gap semiconductor such as silicon carbide (SiC), Gallium nitride series material, and diamond is also applicable. When the wideband gap semiconductor is used as the semiconductor material, a semiconductor device excellent in operation under high voltage, large current, and high temperature compared with a case of using silicone can be obtained. A first main surface which is a lower side surface of the semiconductor substrate 20 in FIG. 1 is referred to as “a rear surface” and a second main surface which is an upper side surface is referred to as “a front surface” hereinafter.

[0029] An N-type drift layer 1 is formed in the semiconductor substrate 20. The semiconductor substrate 20 includes a P-type base layer 2 on a side of a front surface (a side of a second main surface) of the N-type drift layer 1. A peak value of an impurity concentration (referred to as “an impurity peak concentration” hereinafter) of the P-type base layer 2 is set to approximately 8.0×10.sup.16/cm.sup.3 to 5.0×10.sup.17/cm.sup.3 so that gate voltage at a time when current starts flowing from a collector to an emitter of the IGBT, that is to say, a threshold voltage is approximately 6 V.

[0030] The semiconductor substrate 20 includes an N-type emitter layer 3 having a higher impurity peak concentration than the N-type drift layer 1 and a P.sup.+-type diffusion layer 7 having a higher impurity peak concentration than the P-type base layer 2 on a side of a front surface of the P-type base layer 2. These N-type emitter layer 3 and P.sup.+-type diffusion layer 7 are disposed on a surface layer part of the front surface of the semiconductor substrate 20.

[0031] A trench 4 is formed in the front surface of the semiconductor substrate 20 to pass through the N-type emitter layer 3 and the P-type base layer 2 and reach the N-type drift layer 1. A gate insulating film 5 is formed in an inner surface (a side surface and a bottom surface) of the trench 4, and a gate electrode 6 is formed on the gate insulating film 5 to fill the trench 4.

[0032] An interlayer insulating film 8 is formed on the front surface of the semiconductor substrate 20 to cover the gate electrode 6, and an emitter electrode 9 is formed on the interlayer insulating film 8. A contact hole reaching the N-type emitter layer 3 and the P.sup.+-type diffusion layer 7 is formed in the interlayer insulating film 8, and the emitter electrode 9 is connected to the N-type emitter layer 3 and the P.sup.+-type diffusion layer 7 via the contact hole.

[0033] The semiconductor substrate 20 has an N-type buffer layer 10 having a higher impurity peak concentration than the N-type drift layer 1 on a side of a rear surface (a side of a first main surface) of the N-type drift layer 1. The semiconductor substrate 20 includes a P-type collector layer 11 on a side of a rear surface of the N-type buffer layer A collector electrode 12 connected to the P-type collector layer 11 is formed on the rear surface of the semiconductor substrate 20.

[0034] As illustrated in FIG. 1, the N-type buffer layer 10 has a structure that a first buffer layer 101, a second buffer layer 102, a third buffer layer 103, and a fourth buffer layer 104 are disposed in this order from a side of a rear surface of the semiconductor substrate 20. The first buffer layer 101 is formed by implanting phosphorus ions, and the second buffer layer 102, the third buffer layer 103, and the fourth buffer layer 104 are formed by implanting protons. The first buffer layer 101 has an effect of suppressing an occurrence of surge voltage at a time of turn off of the IGBT and an oscillation of voltage and an effect of reducing leakage current as with the second buffer layer 102, the third buffer layer 103, and the fourth buffer layer 104.

[0035] An activation rate of phosphorus by heating is approximately 70 to 100%, and an activation rate of proton by heating is approximately 0.5 to 2%. Thus, the first buffer layer 101 formed by implanting phosphorus ions can be formed in a small ion implantation amount and a short implantation time, and has an effect nearly equal to the buffer layer formed by implanting a large amount of protons for a long time. The N-type buffer layer 10 includes the first buffer layer 101, thus the implantation amount and the time of implantation of protons can be reduced compared with a case where the buffer layer is formed only with proton implantation. As a result, a processing efficiency of a proton implantation machine can be improved.

[0036] FIG. 2 illustrates an impurity concentration profile near the rear surface of the semiconductor substrate 20 (an impurity concentration profile of the P-type collector layer 11, the N-type buffer layer 10, and the N-type drift layer 1) in the IGBT according to the embodiment 1. In a semiconductor device of 1200V withstand voltage class, a specific resistance of the N-type drift layer 1 is 50 Ω.Math.cm to 67 Ω.Math.cm, for example. A sum of a thickness of the N-type drift layer 1 and a thickness of the N-type buffer layer 10 (a sum of a thickness of each of the first buffer layer 101, the second buffer layer 102, the third buffer layer 103, and the fourth buffer layer 104) is 100 μm to 130 μm, for example.

[0037] Herein, the impurity peak concentrations of the first buffer layer 101, the second buffer layer 102, the third buffer layer 103, and the fourth buffer layer 104 are referred to as C1, C2, C3, and C4, respectively. Positions of peaks of the impurity concentrations of the first buffer layer 101, the second buffer layer 102, the third buffer layer 103, and the fourth buffer layer 104 are referred to as P1, P2, P3, and P4, respectively. The position of peak of the impurity concentration expresses a distance (depth) from the rear surface of the semiconductor substrate 20, and is referred to as “the impurity peak position” hereinafter.

[0038] A distance from the impurity peak position P1 of the first buffer layer 101 to the impurity peak position P2 of the second buffer layer 102 is referred to as L12, a distance from the impurity peak position P2 of the second buffer layer 102 to the impurity peak position P3 of the third buffer layer 103 is referred to as L23, and a distance from the impurity peak position P3 of the third buffer layer 103 to the impurity peak position P4 of the fourth buffer layer 104 is referred to as L34. In the IGBT according to the embodiment 1, the N-type buffer layer 10 is made to satisfy a relationship of L23/L12≥3.5.

[0039] Performed is a device simulation for checking an effect by the N-type buffer layer 10 of the IGBT according to the embodiment 1. The simulation is performed on three IGBTs each having an impurity concentration profile near the rear surface of the semiconductor substrate 20 different from each other. FIG. 3 illustrates the impurity concentration profile near the rear surface of the semiconductor substrate 20 (the impurity concentration profile of the P-type collector layer 11, the N-type buffer layer 10, and the N-type drift layer 1) in each of the three IGBTs on which the simulation is performed. Values of L23/L12 in these three IGBTs are 4.28, 2.80, and 1.30, respectively.

[0040] Herein, L12 can be adjusted by the impurity peak position P2 of the second buffer layer 102 located closest to the rear surface of the semiconductor substrate 20 in the buffer layer formed using protons. However, as illustrated in FIG. 4, when the second buffer layer 102 is formed deep and a distance from the impurity peak position P1 of the first buffer layer 101 formed using phosphorus to the impurity peak position P2 of the second buffer layer 102 is increased, current which can be controlled by reverse bias safe operating area (RBSOA) test for examining a breakdown strength of the IGBT decreases. This condition may cause a breakdown of a device when overcurrent flows during an actual operation Thus, a length of L12 is fixed to approximately 3.5 μm in the simulation. However, the effect of suppressing the surge voltage similar to that in the simulation result can be expected even when the impurity peak position P1 of the first buffer layer 101 is 0.5 μm to 2 μm, the impurity peak concentration C1 thereof is 1.0×10.sup.16/cm.sup.3 to 1.0×10.sup.17/cm.sup.3, the impurity peak position P2 of the second buffer layer 102 is 2 μm to 6 μm, and the impurity peak concentration C2 thereof is 5.0×10.sup.14/cm.sup.3 to 2.0×10.sup.15/cm.sup.3.

[0041] The impurity peak position P4 of the fourth buffer layer 104 is determined by a limitation of acceleration voltage of an implantation machine, thus is set as a fixed value in the simulation. Thus, a value of L23+L34 is a fixed value in the simulation. However, the effect similar to that in the simulation result can be expected even when the impurity peak position P4 of the fourth buffer layer 104 is 20 μm to 40 μm and the impurity peak concentration C4 thereof is 1.0×10.sup.14/cm.sup.3 to 1.0×10.sup.14/cm.sup.3.

[0042] FIG. 5 illustrates a result of simulation of a waveform of an emitter-collector voltage (Vce) at a time of turn-off of an IGBT in which the N-type buffer layer 10 is made up of only the first buffer layer 101. In a case where the N-type buffer layer 10 is made up of only the first buffer layer 101, the depletion layer reaches the side of the rear surface at a time when Vce reaches around a peak once and an inflection point appears, thus large surge voltage and a horn (bounce) of voltage occurs in the emitter-collector voltage Vce. This bounce of Vce causes withstand voltage breakdown of the semiconductor device. Thus, a difference between values of peak voltage of Vce before and after the inflection point appears as an index of evaluating a presence or absence of the bounce of Vce. That is to say, ΔVcep=Vcepb−Vcepa is calculated, wherein the peak voltage of Vce before the inflection point appears is Vcepa and the peak voltage of Vce after the inflection point appears is Vcepb. When ΔVcep takes a positive value, it is evaluated that there is a bounce of voltage, and when ΔVcep takes a value equal to or smaller than 0, it is evaluated that there is no bounce of voltage.

[0043] FIG. 6 is a simulation result of the emitter-collector voltage (Vce) at the time of turn off of the three IGBTs illustrated in FIG. 3, and FIG. 7 is a partially-enlarged view thereof. FIG. 8 illustrates a relationship between L23/L12 and ΔVcep obtained from the simulation result. As recognized from FIG. 8, when L23/L12 is equal to or larger than 3.5, ΔVcep takes a negative value, and a bounce of Vce is suppressed.

[0044] FIG. 9 illustrates a relationship between L23/L34 and ΔVcep. As recognized from FIG. 9, when L23/L34 is equal to or larger than 1, ΔVcep takes a negative value, and a bounce of Vce is suppressed.

[0045] The impurity peak concentrations C2, C3, and C4 of the second buffer layer 102, the third buffer layer 103, and the fourth buffer layer 104, respectively, preferably satisfy a relationship of C2>C3>C4 to suppress the surge voltage at the time of turn off. It is preferable that the impurity peak concentration C1 of the first buffer layer 101 is 1.0×10.sup.16/cm.sup.3 to 1.0×10.sup.17/cm.sup.3, the impurity peak concentration C2 of the second buffer layer 102 is 5.0×10.sup.14/cm.sup.3 to 2.0×10.sup.15/cm.sup.3, and the impurity peak concentration C3 of the third buffer layer 103 is 2.0×10.sup.14/cm.sup.3 to 1.5×10.sup.15/cm.sup.3, and the impurity peak concentration C4 of the fourth buffer 104 is 1.0×10.sup.14/cm.sup.3 to 1.0×10.sup.15/cm.sup.3.

[0046] The impurity concentration in a depth between the impurity peak position P2 of the second buffer layer 102 and the impurity peak position P3 of the third buffer layer 103 and the impurity concentration in a depth between the impurity peak position P3 of the third buffer layer 103 and the impurity peak position P4 of the fourth buffer layer 104 are preferably higher than the impurity concentration of the N-type drift layer 1 to dissolve a crystal defect region.

[0047] When an extension of the impurity in the first buffer layer 101, the second buffer layer 102, the third buffer layer 103, and the fourth buffer layer 104 in a depth direction is evaluated with a half-value width in which the impurity concentration is half the peak (referred to as “the impurity half-value width” hereinafter), an impurity half-value width W1 of the first buffer layer 101 is approximately 0.3 μm, an impurity half-value width W2 of the second buffer layer 102 is approximately 2.0 μm, an impurity half-value width W3 of the third buffer layer 103 is approximately 2.4 μm, and an impurity half-value width W4 of the fourth buffer layer 104 is approximately 2.9 μm. The impurity half-value widths W1, W2, W3, and W4 of the first buffer layer 101, the second buffer layer 102, the third buffer layer 103, and the fourth buffer layer 104, respectively, satisfy a relationship of W1<W2<W3<W4.

[0048] In this manner, the first buffer layer 101, the second buffer layer 103, the third buffer layer 103, and the fourth buffer layer 104 have the higher impurity peak concentration and the smaller extension of the impurity in the depth direction (the impurity half-value width) as they are located closer to the side of the rear surface of the semiconductor substrate 20. Particularly, an envelope curve connecting the impurity peak concentrations C2, C3, and C4 of the second buffer layer 102, the third buffer layer 103, and the fourth buffer layer 104 formed using the same impurity (proton) is close to Gaussian distribution expressed by the following expression.

[00001]$\begin{array}{cc}C\left(x,t\right)=\frac{S}{\sqrt{\pi Dt}}\exp \left(-\frac{x^2}{4Dt}\right)& \left[\mathrm{Expression}1\right]\end{array}$

[0049] In the above expression, C indicates a dopant concentration per unit area, D indicates a diffusion coefficient, S indicates a dopant total amount per unit area, t indicates a time, and x indicates a depth from the rear surface of the semiconductor substrate 20. When the second buffer layer 102, the third buffer layer 103, and the fourth buffer layer 104 satisfy this relationship, the effect of suppressing the surge voltage at the time of turn off is obtained even if the impurity peak concentrations C2, C3, and C4 are reduced. Thus, a processing efficiency of a proton implantation machine can be improved by reducing the implantation amount of protons. Specifically, the impurity peak concentrations C2, C3, and C4 of the second buffer layer 102, the third buffer layer 103, and the fourth buffer layer 104 may be equal to or smaller than 2.0×10.sup.15/cm.sup.3.

[0050] When the N-type buffer layer 10 satisfies a relationship of L23/L12≥3.5, it is confirmed by the simulation that a semiconductor device having at least one of configurations (a) to (g) described hereinafter has an effect of suppressing the surge voltage inducing an oscillation of turn off.

(a) Withstand voltage is equal to or smaller than 750V, a specific resistance of the N-type drift layer 1 is equal to or larger than 20 Ω.Math.cm and equal to or smaller than 40 Ω.Math.cm, and a sum of a thickness of the N-type drift layer 1 and a thickness of the N-type buffer layer 10 is equal to or larger than 50 μm and equal to or smaller than 80 μm,
(b) Withstand voltage is 1200V, a specific resistance of the N-type drift layer 1 is equal to or larger than 50 Ω.Math.cm and equal to or smaller than 90 Ω.Math.cm, and a sum of a thickness of the N-type drift layer 1 and a thickness of the N-type buffer layer 10 is equal to or larger than 100 μm and equal to or smaller than 130 μm,
(c) Withstand voltage is 1700V, a specific resistance of the N-type drift layer 1 is equal to or larger than 90 Ω.Math.cm and equal to or smaller than 130 Ω.Math.cm, and a sum of a thickness of the N-type drift layer 1 and a thickness of the N-type buffer layer 10 is equal to or larger than 170 μm and equal to or smaller than 210 μm,
(d) Withstand voltage is 2000V, a specific resistance of the N-type drift layer 1 is equal to or larger than 130 Ω.Math.cm and equal to or smaller than 180 Ω.Math.cm, and a sum of a thickness of the N-type drift layer 1 and a thickness of the N-type buffer layer 10 is equal to or larger than 200 μm and equal to or smaller than 260 μm,
(e) Withstand voltage is 3300V, a specific resistance of the N-type drift layer 1 is equal to or larger than 200 Ω.Math.cm and equal to or smaller than 350 Ω.Math.cm, and a sum of a thickness of the N-type drift layer 1 and a thickness of the N-type buffer layer 10 is equal to or larger than 340 μm and equal to or smaller than 420 μm,
(f) Withstand voltage is 4500V, a specific resistance of the N-type drift layer 1 is equal to or larger than 300 Ω.Math.cm and equal to or smaller than 450 Ω.Math.cm, and a sum of a thickness of the N-type drift layer 1 and a thickness of the N-type buffer layer 10 is equal to or larger than 420 μm and equal to or smaller than 540 μm, and
(g) Withstand voltage is 6500V, a specific resistance of the N-type drift layer 1 is equal to or larger than 600 Ω.Math.cm and equal to or smaller than 900 Ω.Math.cm, and a sum of a thickness of the N-type drift layer 1 and a thickness of the N-type buffer layer 10 is equal to or larger than 580 μm and equal to or smaller than 720 μm.

[0051] The thickness of the N-type buffer layer 10 is equal to a sum of each thickness of the first buffer layer 101, the second buffer layer 102, the third buffer layer 103, and the fourth buffer layer 104.

[0052] A method of manufacturing the IGBT according to the embodiment 1 is described herein. A method of forming a structure of the side of the front surface of the semiconductor substrate 20 may be the same as the method of manufacturing a known IGBT, thus described herein is a method of forming a structure of the side of the rear surface of the semiconductor substrate 20 (the N-type buffer layer 10, the P-type collector layer 11, and the collector electrode 12).

[0053] FIG. 10 illustrates a state where a process of forming the side of the front surface of the semiconductor substrate 20 is completed. At this point of time, the thickness of the semiconductor substrate 20 (wafer) is substantially the same as a bare wafer, that is approximately 700 μm. The side of the rear surface of the semiconductor substrate 20 in the state illustrated in FIG. 10 is ground by a grinder or wet etching to reduce the thickness of the semiconductor substrate 20 to a desired thickness.

[0054] Subsequently, as illustrated in FIG. 12, protons for forming the second buffer layer 102, the third buffer layer 103, and the fourth buffer layer 104 are implanted from the rear surface of the semiconductor substrate 20. At this time, acceleration voltage of proton implantation is changed with three levels, thus protons are implanted in depths corresponding to the second buffer layer 102, the third buffer layer 103, and the fourth buffer layer 104, respectively. Alternatively, the implantation depth of protons may be controlled by changing an implantation angle or using an absorber without changing the acceleration voltage, and in that case, an implantation time can also be reduced.

[0055] Subsequently, furnace annealing is performed at approximately 300° C. to 500° C. to activate the implanted protons. Accordingly, as illustrated in FIG. 13, the second buffer layer 102, the third buffer layer 103, and the fourth buffer layer 104 are formed in depths different from each other.

[0056] Next, as illustrated in FIG. 14, phosphorus for forming the first buffer layer 101 is implanted from the rear surface of the semiconductor substrate 20. Then, the implanted phosphorus is activated by laser annealing. The first buffer layer 101 is thereby formed in a shallow position on the side of the rear surface of the semiconductor substrate 20.

[0057] Next, as illustrated in FIG. 16, boron for forming the P-type collector layer 11 is implanted from the rear surface of the semiconductor substrate 20. Then, the implanted boron is activated by laser annealing. The P-type collector layer 11 is thereby formed on the surface layer part on the side of the rear surface as illustrated in FIG. 17.

[0058] An order of performing the process of forming the second buffer layer 102, the third buffer layer 103, and the fourth buffer layer 104, the process of forming the first buffer layer 101, and the process of forming the P-type collector layer 11 may be rearranged, and it is sufficient that the processes are performed in a simple order in manufacturing.

[0059] Subsequently, a film of Al/Ti/Ni/Au or AlSi/Ti/Ni/Au, for example, is formed on the rear surface of the semiconductor substrate 20 by sputtering method to form the collector electrode 12 as illustrated in FIG. 18. Finally, thermal processing is performed to reduce a contact resistance of the P-type collector layer 11 and the collector electrode 12. The IGBT illustrated in FIG. 1 is thereby completed by the above processing.

[0060] As described above, according to the semiconductor device of the embodiment 1, the N-type buffer layer 10 includes the first buffer layer 101 formed using phosphorus, thus the concentration of proton in the second buffer layer 102, the third buffer layer 103, and the fourth buffer layer 104 formed using proton can be reduced, and the implantation amount of protons for forming the N-type buffer layer 10 can be reduced. The number of the first buffer layers 101, the second buffer layers 102, the third buffer layers 103, and the fourth buffer layers 104 and the distance therebetween are set as described above, thus the extension of the depletion layer can be gradually stopped, and the surge voltage at the time of turn off (at the time of applying the voltage) can be suppressed.

[0061] Although the illustration is omitted, the semiconductor device may be an IGBT having a structure that an N+-type carrier accumulation layer having a higher impurity peak concentration than the N-type drift layer 1 is provided between the P-type base layer 2 and the N-type drift layer 1, that is to say, a carrier stored trench-gate bipolar transistor (CSTBT).

Embodiment 2

[0062] The IGBT is described as the example of the semiconductor device in the embodiment 1, however, a diode is used as the semiconductor device in the embodiment 2. FIG. 19 is a cross-sectional view of a major part of a diode which is a semiconductor device according to the embodiment 2.

[0063] As illustrated in FIG. 19, a semiconductor substrate 20 constituting a diode has a P-type anode layer 13 on the side of the front surface of the N-type drift layer 1. An anode electrode 14 connected to the P-type anode layer 13 is formed on the front surface of the semiconductor substrate 20. The semiconductor substrate 20 includes the N-type buffer layer 10 similar to that in the embodiment 1, that is to say, the N-type buffer layer 10 made up of the first buffer layer 101, the second buffer layer 102, the third buffer layer 103, and the fourth buffer layer 104. The semiconductor substrate 20 further includes an N-type cathode layer 15 on the side of the rear surface of the N-type drift layer 1. A cathode electrode 16 connected to the N-type cathode layer 15 is formed on the rear surface of the semiconductor substrate 20.

[0064] Obtained according to the diode of the embodiment 2 is an effect that an oscillation at a time of recovery of the diode is suppressed as with the case where the oscillation of voltage at the time of turn off is suppressed in the IGBT according to the embodiment 1.

[0065] The structure on the side of the rear surface of the diode according to the embodiment 2 can be formed by the method similar to the method of forming the structure on the side of the rear surface of the IGBT described in the embodiment 1. That is to say, in the method of forming the structure on the side of the rear surface of the IGBT described in the embodiment 1, it is sufficient that the N-type cathode layer 15 is formed in place of the P-type collector layer 11, and the cathode electrode 16 is formed in place of the collector electrode 12 of the IGBT.

[0066] Although the illustration is omitted, the diode in FIG. 19 may also be provided with the trench 4, the gate insulating film 5, and the gate electrode 6 similar to those in FIG. 1 (the gate electrode 6 provided in the diode is a dummy gate electrode). In that case, the trench 4 is formed to pass through the P-type anode layer 13 and reach the N-type drift layer 1.

[0067] The diode in FIG. 19 is a PN junction diode, but may be a merged PiN Schottky (MPS) diode having an MPS structure in which a PN junction diode and a Schottky barrier diode are combined. In the diode in FIG. 19, the N-type cathode layer 15 is provided over the whole side of the rear surface of the first buffer layer 101, however, also applicable is a structure that an N-type cathode layer and a P-type cathode layer are alternately provided on the side of the rear surface of the first buffer layer 101. The semiconductor device may be a reverse conducting IGBT (RC-IGBT) in which a region where an IGBT is formed and a region where a diode is formed are provided in one semiconductor substrate 20. Also in such various types of diode, the N-type buffer layer 10 made up of the first buffer layer 101, the second buffer layer 102, the third buffer layer 103, and the fourth buffer layer 104 is provided, thus the effect of suppressing the oscillation at the time of recovery is obtained.

[0068] Each embodiment can be arbitrarily combined, or each embodiment can be appropriately varied or omitted.

[0069] While the disclosure has been shown and described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is therefore understood that numerous modifications and variations can be devised.