Structures and formation methods of a chip package structure are provided. The chip package structure includes adjacent first and second semiconductor dies bonded over an interposer substrate. The chip package structure also includes an insulating layer formed over the interposer substrate. The insulating layer has a first portion surrounding the first and second semiconductor dies and a second portion extending between a first sidewall of the first semiconductor die and a second sidewall of the second semiconductor die, and between the interposer substrate and the first and second semiconductor dies. The lateral distance from the top end of the first sidewall to the top end of the second sidewall is greater than the lateral distance from the bottom end of the first sidewall to the bottom end of the second sidewall.

A semiconductor device includes a substrate, a semiconductor layer that is provided on the substrate and includes channel layers that are stacked, a source electrode and a drain electrode that are electrically connected to the channel layers, and gate electrodes that are provided between the source electrode and the drain electrode, are arranged in a direction intersecting with a direction from the source electrode to the drain electrode, and are embedded in the semiconductor layer so as to extend from a top face of the semiconductor layer to at least a channel layer closest to the substrate, wherein a width between two adjacent gate electrodes of the gate electrodes in a channel layer farther from the substrate of two channel layers of the channel layers, is narrower than a width between the two adjacent gate electrodes in a channel layer closer to the substrate of the two channel layers.

A semiconductor package includes a semiconductor device, an encapsulating material, and a redistribution structure. The semiconductor device includes a chamfer disposed on one of a plurality of side surfaces of the semiconductor device. The encapsulating material encapsulates the semiconductor device. The redistribution structure is disposed over the encapsulating material and electrically connected to the semiconductor device.

A semiconductor device has a cell part and a terminal part set in the device. The terminal part encloses the cell part. The semiconductor device includes a first electrode, a first semiconductor layer of a first conductive type, a second semiconductor layer of a second conductive type, and an insulating layer. The first semiconductor layer is formed above the first electrode. The second semiconductor layer is provided in an upper portion of the first semiconductor layer, and has an impurity concentration profile along a vertical direction including a plurality of peaks. The insulating layer is provided on the second semiconductor layer.

A method forms a part of a power semiconductor device. The method includes homoepitaxially forming two silicon carbide layers on a first side of a silicon carbide substrate and forming a pattern of pits on a second side of the silicon carbide substrate. The two layers include a buffer layer, on the first side of the silicon carbide substrate, and have a same doping type of the silicon carbide substrate and a doping concentration equal to or greater than 10.sup.17 cm.sup.−3 in order to increase the quality of at least one subsequent SiC layer. The two layers include an etch stopper layer, being deposited on the buffer layer and has a same doping type as the buffer layer but a lower doping concentration in order to block a trenching process. The pattern of pits, obtained by electrochemical etching, extends completely thorough the silicon carbide substrate and the buffer layer.

A semiconductor device and fabricating method thereof is disclosed. The method comprises depositing epitaxial layers over a silicon substrate to form a semiconductor layer surface; forming at least one mesa portion on the semiconductor layer surface; depositing a metal stack on the semiconductor layer surface; subjecting the semiconductor layer surface to a rapid thermal annealing system for a two-step ohmic contact annealing in H.sub.2/N.sub.2 forming gas (FG) and then nitrogen; subjecting the semiconductor layer surface to an oxygen plasma treatment; and depositing a T-shaped metal gate on the semiconductor layer surface. A semiconductor device comprises a semiconductor layer surface having an epitaxial layer disposed over a silicon substrate; at least one mesa portion formed on the semiconductor layer surface; a metal stack, disposed on the semiconductor layer surface, and sequentially annealed in FG and nitrogen; and a T-shaped metal gate on the semiconductor layer surface.

A switching device including a GaN substrate; an unintentionally doped GaN layer on a first surface of the GaN substrate; a regrown unintentionally doped GaN layer on the unintentionally doped GaN layer; a regrowth interface between the unintentionally doped GaN layer and the regrown unintentionally doped GaN layer; a p-GaN layer on the regrown unintentionally doped GaN layer; a first electrode on the p-GaN layer; and a second electrode on a second surface of the GaN substrate.

A semiconductor device is provided. The semiconductor device includes a bottom source/drain; a top source/drain; a fin provided between the bottom source/drain and the top source/drain, the fin including a first fin structure and a second fin structure that are symmetric to each other in a plan view. Each of the first and second fin structures includes a main fin extending laterally in a first direction, and first and second extension fins extending laterally from the main fin in a second direction perpendicular to the first direction. The main fin extends laterally in the first direction beyond where the first and second extension fins connect to the main fin.

A semiconductor device includes a chip that includes a mounting surface, a non-mounting surface, and a side wall connecting the mounting surface and the non-mounting surface and has an eaves portion protruding further outward than the mounting surface at the side wall and a metal layer that covers the mounting surface.

Disclosed is a semiconductor device comprising an active region that protrudes upwardly from a substrate, a plurality of channel patterns that are spaced apart from each other in a first direction on the active region, and a gate electrode that extends in the first direction on the active region and covers the plurality of channel patterns. Each of the plurality of channel patterns includes a plurality of semiconductor patterns that are spaced apart from each other in a direction perpendicular to a top surface of the active region. The gate electrode covers the top surface of the active region between the plurality of channel patterns.